參數(shù)資料
型號: HN29WT800
廠商: Hitachi,Ltd.
英文描述: 1048576-word x 8-bit / 524288-word x 16-bit CMOS Flash Memory
中文描述: 1048576字× 8位/ 524288字× 16位CMOS閃存
文件頁數(shù): 14/37頁
文件大小: 170K
代理商: HN29WT800
HN29WT800 Series, HN29WB800 Series
14
Standby:
When
CE
is at V
IH
, the device is in the standby mode and its power consumption is reduced. Data
input/output are in a high impedance (High-Z) state. If the memory is deselected during block erase or
program, the internal control circuits remain active and the device consume normal active power until the
operation completes.
Deep Powerdown:
When
RP
is at V
IL
, the device is in the deep powerdown mode and its power
consumption is substantially low. During read modes, the memory is deselected and the data input/output are
in a high impedance (High-Z) state. After return from powerdown, the CUI is reset to Read Array and the
Status Register is cleared to value 80H. During block erase or program modes,
RP
low will abort either
operation. Memory array data of the block being altered become invalid.
Functional Description
The device operations are selected by writing specific software command into the CUI.
Read Array Command (FFH):
The device is in read array mode on initial device power up and after exit
from deep power down, or by writing FFH to the CUI. The device remains in Read Array mode until the
other commands are written.
Read Device Identifier Command (90H):
Though PROM programmers can normally read device identifier
codes by raising A9 to high voltage, multiplexing high voltage onto address lines is not desired for micro-
processor system. It is an other means to read device identifier codes that Read Device Identifier Code
Command (90H) is written to the command latch. Following the write of the Read Device Identifier
command of 90H, the manufacturer code and the device code can be read from addresses 00000H and
00001H, respectively.
Read Status Register Command (70H):
The Status Register is read after writing the read status register
command of 70H to the CUI. The contents of Status Register are latched on the later falling edge of
OE
or
CE
. So
CE
or
OE
must be toggled every status read.
Clear Status Register Command (50H):
The Erase Status and Program Status bits are set to High by the
Write State Machine and can be reset by the Clear Status Register command of 50H. These bits indicates
various failure conditions.
Block Erase/Confirm Command (20H/D0H):
Automated block erase is initiated by writing the Block
Erase of 20H followed by the Confirm command of D0H. An address within the block to be erased is
required. The WSM executes iterative erase pulse application and erase verify operation.
Suspend/Resume Command (B0H/D0H):
Writing the suspend command of B0H during block erase
operation interrupts the block erase operation and allows read out from another block of memory. Writing the
suspend command of B0H during program operation interrupts the program operation and allows read out
from another block of memory. The device continues to output status register data when read, after the
suspend command is written to it. Polling the WSM status and suspend status bits will determine when the
erase operation or program operation has been suspended. At this point, writing of the read array command to
the CUI enables reading data from blocks other than that which is suspended. When the resume command of
D0H is written to the CUI, the WSM will continue with the erase or program processes.
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