參數資料
型號: HN29WT800
廠商: Hitachi,Ltd.
英文描述: 1048576-word x 8-bit / 524288-word x 16-bit CMOS Flash Memory
中文描述: 1048576字× 8位/ 524288字× 16位CMOS閃存
文件頁數: 13/37頁
文件大?。?/td> 170K
代理商: HN29WT800
HN29WT800 Series, HN29WB800 Series
13
Device Identifier Mode
The device identifier mode allows the reading out of binary codes that identify manufacturer and type of
device, from outputs of Flash Memory. By this mode, the device will be automatically matched its own
corresponding erase and programming algorithm.
HN29WT800 Series, HN29WB800 Series Identifier Code
Pins
A0
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Hex. data
Manufacturer code
0
0
0
0
0
0
1
1
1
07H
Device code (T series)
1
1
0
0
0
0
1
0
1
85H
Device code (B series)
Notes: 1. Device identifier code can be read out by using the read identified codes command.
2. In the word mode, the same data as I/O7 to I/O0 is read out from I/O15 to I/O8.
3. A9 = V
mode. A9 = 11.5 V to 13.0 V. Set A9 to V
min 200 ns before falling edge of
CE
in ready
status. Min 200 ns after return to V
HH
, device can’t be accessed. A1 to A8, A10 to A18,
CE
,
OE
, =
V
IL
,
WE
= V
IH
, I/O15/A-1 = V
IL
(
BYTE
= L).
1
1
0
0
0
0
1
1
0
86H
Operations of the HN29WT800 Series, HN29WB800 Series
The HN29WT800 Series, HN29WB800 Series include on-chip program/erase control circuitry. The Write
State Machine (WSM) controls block erase and page program operations. Operational modes are selected by
the commands written to the Command User Interface (CUI). The Status Register indicates the status of the
WSM and when the WSM successfully completes the desired program or block erase operation. A Deep
Powerdown mode is enabled when the
RP
pin is at V
SS
minimizing power consumption.
Read:
The HN29WT800 Series, HN29WB800 Series have three read modes, which accesses to the memory
array, the Device Identifier and the Status Register. The appropriate read command are required to be written
to the CUI. Upon initial device powerup or after exit from deep powerdown, the HN29WT800 Series,
HN29WB800 Series automatically reset to read array mode. In the read array mode, low level input to
CE
and
OE
, high level input to
WE
and
RP
, and address signals to the address inputs (A0 to A18) output the data
of the addressed location to the data input/output (I/O0 to I/O15).
Write:
Writes to the CUI enable reading of memory array data, device identifiers and reading and clearing of
the Status Register, they also enable block erase and program. The CUI is written by bringing
WE
to low
level, while
CE
is at low level and
OE
is at high level. Addresses and data are latched on the earlier rising
edge of
WE
and
CE
. Standard micro-processor write timings are used.
Output Disable:
When
OE
is at V
IH
, output from the device is disabled. Data input/output are in a high
impedance (High-Z) state.
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