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參數(shù)資料
| 型號： | HM66WP18513BP-65 |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 ZBT SRAM, 6.5 ns, PBGA119 |
| 封裝： | BGA-119 |
| 文件頁數(shù)： | 3/31頁 |
| 文件大?。?/td> | 268K |
| 代理商： | HM66WP18513BP-65 |
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HM66WP18513, HM66WP36257
Rev.0.3, Mar. 2002, page 11 of 31
Synchronous Truth Table
Operation
Address
CE1
CE1 CE3
CE3
CE3 CE2
ADV
/
LD
LD CEN
CEN
CEN W
W
WE
EE
EB
BB
BW
W
Wm
m
mOE
OE
OE CLK DQ
Deselected cycle, power-down
None
H
××
LL
××
×
L-H
High-Z
Deselected cycle, power-down
None
×
H
×
LL
××
×
L-H
High-Z
Deselected cycle, power-down
None
××
LL
L
××
×
L-H
High-Z
WRITE cycle, begin burst
External L
L
H
L
×
L-H
D
NOP/WRITE Abort, begin burst
External L
L
H
L
H
×
L-H
High-Z
READ cycle, begin burst
External L
L
H
L
H
×
LL-H
Q
Dummy READ cycle, begin burst
External L
L
H
L
H
×
H
L-H
High-Z
WRITE cycle, continue burst
Next
××
×
HL
×
L
×
L-H
D
WRITE Abort, continue burst
Next
××
×
HL
×
H
×
L-H
High-Z
READ cycle, continue burst
Next
××
×
HL
××
LL-H
Q
Dummy READ cycle, continue burst Next
××
×
HL
××
H
L-H
High-Z
WRITE cycle, suspend
Current
××
×
H
××
×
L-H
-
READ cycle, suspend
Current
××
×
H
××
LL-H
Q
Dummy READ cycle, suspend
Current
××
×
H
××
H
L-H
High-Z
Notes: 1. H means logic HIGH, L means logic LOW.
× means H or L. WE = L means any one or more
byte write enable signals (
BWa, BWb, BWc or BWd) are LOW. Write = H means all byte write
enable signals are HIGH.
2.
BWa enables write to Bytea (DQa0 to DQa8). BWb enables write to Byteb (DQb0 to DQb8).
BWc enables write to Byte2 (DQc0 to DQc8). BWd enables write to Byted (DQd0 to DQd8).
3. All inputs except
OE and ZZ must meet setup and hold times around the rising edge (LOW to
HIGH) of CLK.
4. A WRITE is performed by setting one or more byte write enable signals and
WE LOW for the
subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification.
5. The status for DQ described in this synchronous truth table appears one clock after the cycle in
which the Read or Write command is asserted.
6.
If ADV/
LD is sampled High that it is continue burst cycle follows before the operation cycle.
7.
Wait states are inserted by
CEN = High. When CEN is sampled High after Read cycle, the
Read data is maintain as output data. When
CEN is sampled High after Write cycle, the Write
Input Data is ignored and is maintained High-Z. Refer to Timing diagram for clarification.
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