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參數(shù)資料
| 型號： | HM66WP18513BP-65 |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 ZBT SRAM, 6.5 ns, PBGA119 |
| 封裝： | BGA-119 |
| 文件頁數(shù)： | 16/31頁 |
| 文件大?。?/td> | 268K |
| 代理商： | HM66WP18513BP-65 |
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HM66WP18513, HM66WP36257
Rev.0.3, Mar. 2002, page 23 of 31
Boundary Scan Test Access Port Operations (only BGA)
Overview
In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary
scan test access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 - 1990.
But does not implement all of the functions required for 1149.1 compliance The HM66WP series contains a
TAP controller. Instruction register, Boundary scans register, Bypass register and ID register.
Test Access Port Pins
Symbol I/O
Name
TCK
Test Clock
TMS
Test Mode Select
TDI
Test Data In
TDO
Test Data Out
Notes: This Device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1.
To disable the TAP, TCK must be connected to Vss. TDO should be left unconnected.
To test Boundary scan, ZZ pin need to be kept below V
IL.
TAP DC Operating Characteristics
(Ta = 0°C to 70°C)
Parameter
Symbol
Min
Max
Notes
Boundary scan Input High voltage (3.3V I/O)
V
IH
2.0 V
V
DD +0.3V
Boundary scan Input High voltage (2.5V I/O)
V
IH
1.7 V
V
DD +0.3V
Boundary scan Input Low voltage (3.3V I/O)
V
IL
–0.3 V
0.8 V
Boundary scan Input Low voltage (2.5V I/O)
V
IL
–0.3 V
0.7 V
Boundary scan Input Leakage Current
I
LI
–5 A
+5 A
1
Boundary scan Output Leakage Current
I
Lo
–5 A
+5 A
1
Boundary scan Output Low voltage (3.3V/2.5V)
V
OL
—
0.4 V/0.4 V
2
Boundary scan Output High voltage (3.3V/2.5V)
V
OH
2.4 V/2.0V
—
3
Notes: 1. 0
≤ Vin ≤ V
DD for all logic input pin
2. I
OL = –8 mA at VDD = 3.3 V , IOL = –1 mA at VDD = 2.5 V.
3. I
OH = 4 mA at VDD = 3.3 V , IOH = 1 mA at VDD = 2.5 V.
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