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參數(shù)資料
| 型號： | HM62W8128DLR-7 |
| 元件分類： | SRAM |
| 英文描述： | STANDARD SRAM, PDSO32 |
| 封裝： | 8 X 20 MM, PLASTIC, REVERSE, TSOP1-32 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 142K |
| 代理商： | HM62W8128DLR-7 |
HM62W8128D Series
12
Low V
CC Data Retention Characteristics (Ta = –20 to +70°C)
Parameter
Symbol
Min
Typ*
5
Max
Unit
Test conditions*
4
V
CC for data retention
V
DR
2.0
—
V
Vin
≥ 0V
(1) 0 V
≤ CS2 ≤ 0.2 V or
(2) CS2
≥ V
CC – 0.2 V
CS1
≥ V
CC – 0.2 V
Data retention current
I
CCDR*
1
—
0.8
20
AV
CC = 3.0 V, Vin ≥ 0 V
(1) 0 V
≤ CS2 ≤ 0.2 V or
(2) CS2
≥ V
CC – 0.2 V,
CS1
≥ V
CC – 0.2 V
I
CCDR*
2
—
0.8
10
A
I
CCDR*
3
—
0.5
2
A
Chip deselect to data retention time
t
CDR
0
—
ns
See retention waveform
Operation recovery time
t
R
t
RC*
6
——
ns
Notes: 1. This characteristic is guaranteed only for L-version, 10
A max. at Ta = –20 to +40°C.
2. This characteristic is guaranteed only for L-SL-version, 3
A max. at Ta = –20 to +40°C.
3. This characteristic is guaranteed only for L-UL-version, 1
A max. at Ta = –20 to +40°C.
4. CS2 controls address buffer,
WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address,
WE, OE, CS1, I/O) can be in the high impedance state.
If
CS1 controls data retention mode, CS2 must be CS2
≥ V
CC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V.
The
other input levels (address,
WE, OE, I/O) can be in the high impedance state.
5. Typical values are at V
CC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
6. t
RC = read cycle time.
Low V
CC Data Retention Timing Waveform (1) (CS1 Controlled)
VCC
3.0 V
2.4 V
0 V
CS1
tCDR
tR
CS1
≥ V
CC – 0.2 V
VDR
Data retention mode
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