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參數(shù)資料
| 型號： | HM62W8128DLR-7 |
| 元件分類： | SRAM |
| 英文描述： | STANDARD SRAM, PDSO32 |
| 封裝： | 8 X 20 MM, PLASTIC, REVERSE, TSOP1-32 |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 142K |
| 代理商： | HM62W8128DLR-7 |
HM62W8128D Series
7
AC Characteristics (Ta = –20 to +70
°C, V
CC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
Input pulse levels: V
IL = 0.4 V, VIH = 2.4 V
Input rise and fall time: 5 ns
Input timing reference levels: 1.4 V
Output timing reference level: 1.4 V
Output load (Including scope and jig)
Dout
50pF
R1
V
TM
V
TM = 2.8 V
R2
R1 = 3070
R2 = 3150
Read Cycle
HM62W8128D
-5
-7
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read cycle time
t
RC
55
—
70
—
ns
Address access time
t
AA
—
55
—
70
ns
Chip select access time
t
ACS1
—
55
—
70
ns
t
ACS2
—
55
—
70
ns
Output enable to output valid
t
OE
—
30
—
35
ns
Output hold from address change
t
OH
10
—
10
—
ns
Chip selection to output in low-Z
t
CLZ1
10
—
10
—
ns
2, 3
t
CLZ2
10
—
10
—
ns
2, 3
Output enable to output in low-Z
t
OLZ
5
—
5
—
ns
2, 3
Chip deselection to output in high-Z
t
CHZ1
0
20
0
25
ns
1, 2, 3
t
CHZ2
0
20
0
25
ns
1, 2, 3
Output disable to output in high-Z
t
OHZ
0
20
0
25
ns
1, 2, 3
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