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參數(shù)資料
| 型號： | HM62W8128DLR-7 |
| 元件分類： | SRAM |
| 英文描述： | STANDARD SRAM, PDSO32 |
| 封裝： | 8 X 20 MM, PLASTIC, REVERSE, TSOP1-32 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 142K |
| 代理商： | HM62W8128DLR-7 |
HM62W8128D Series
3
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CS2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A3
(Top view)
32-pin TSOP (Normal Type TSOP)
32-pin SOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
A11
A9
A8
A13
WE
CS2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
32-pin TSOP (Reverse Type TSOP)
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
V
CC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
(Top view)
Pin Description
Pin name
Function
A0 to A16
Address input
I/O0 to I/O7
Data input/output
CS1
Chip select 1
CS2
Chip select 2
WE
Write enable
OE
Output enable
V
CC
Power supply
V
SS
Ground
NC
No connection
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