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參數(shù)資料
| 型號(hào)： | HM5165805FLJ-5 |
| 元件分類： | DRAM |
| 英文描述： | 8M X 8 EDO DRAM, 50 ns, PDSO32 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-32 |
| 文件頁數(shù)： | 7/35頁 |
| 文件大?。?/td> | 477K |
| 代理商： | HM5165805FLJ-5 |
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HM5164805F Series, HM5165805F Series
15
Self Refresh Mode (L-version)
HM5164805FL/HM5165805FL
-5
-6
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
RAS pulse width (self refresh)
t
RASS
100
—
100
—
s25
RAS precharge time (self refresh)
t
RPS
90
—
110
—
ns
25
CAS hold time (self refresh)
t
CHS
–50
—
–50
—
ns
Notes: 1. AC measurements assume t
T = 2 ns.
2. An initial pause of 200
s is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing
RAS-only refresh or CAS-before-RAS refresh).
3. Operation with the t
RCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if t
RCD is greater than the specified tRCD (max) limit, than the access time is
controlled exclusively by t
CAC.
4. Operation with the t
RAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if t
RAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by t
AA.
5. Either t
OED or tCDD must be satisfied.
6. Either t
DZO or tDZC must be satisfied.
7. V
IH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between V
IH (min) and VIL (max).
8. Assumes that t
RCD ≤ tRCD (max) and tRAD ≤ tRAD (max).
If t
RCD or tRAD is greater than the maximum
recommended value shown in this table, t
RAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that t
RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11. Assumes that t
RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12. Either t
RCH or tRRH must be satisfied for a read cycles.
13. t
OFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the
open circuit condition and are not referred to output voltage levels.
14. t
WCS, t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters.
They are included in the
data sheet as electrical characteristics only; if t
WCS ≥ tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t
RWD
≥ t
RWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥
t
CPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
15. t
DS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in
delayed write or read-modify-write cycles.
16. t
RASP defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among t
AA, t CAC and t CPA.
18. In delayed write or read-modify-write cycles,
OE must disable output buffer prior to applying data
to the device.
19. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large V
CC/VSS line noise, which causes to degrade VIH min/VIL max
level.
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