參數(shù)資料
型號(hào)： HFA3824A
廠商： Intersil Corporation
元件分類： 基帶處理器
英文描述： Direct Sequence Spread Spectrum Baseband Processor
中文描述： 直接序列擴(kuò)頻基帶處理器
文件頁(yè)數(shù)： 32/40頁(yè)
文件大小： 271K
代理商： HFA3824A
2-130
CONFIGURATION REGISTER 25 ADDRESS (64h) RX SIGNAL QUALITY 1 ACQ READ (LOW)
Bits 0 - 7
This register contains the lower byte bits (0 - 7) of the measured signal quality threshold for the bit sync amplitude used for
acquisition. This register combined with the higher byte represents a 15-bit value, of the measured bit sync amplitude. This
measurement is made at each antenna dwell and is the result of the best antenna.
CONFIGURATION REGISTER 26 ADDRESS (68h) RX SIGNAL QUALITY 1 DATA THRESHOLD (HIGH)
Bits 0 - 7
This control register contains the upper byte bits (8-14) of the bit sync amplitude signal quality threshold used for drop lock
decisions. This register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude signal
quality measurements, made every 128 symbols. These thresholds set the drop lock probability. A higher value will increase
the probability of dropping lock.
CONFIGURATION REGISTER ADDRESS 27 (6Ch) RX SIGNAL QUALITY 1 DATA THRESHOLD (LOW)
Bits 0 - 7
This control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for drop lock
decisions. This register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude signal
quality measurements, made every 128 symbols.
CONFIGURATION REGISTER 28 ADDRESS (70h) RX SIGNAL QUALITY 1 DATA (high) THRESHOLD READ (HIGH)
Bits 0 - 7
This status register contains the upper byte bits (8-14) of the measured signal quality of bit sync amplitude used for drop lock
decisions. This register combined with the lower byte represents a 15-bit value, representing the measured signal quality for
the bit sync amplitude. This measurement is made every 128 symbols.
CONFIGURATION REGISTER 29 ADDRESS (74h) RX SIGNAL QUALITY 1 DATA THRESHOLD READ (LOW)
Bits 0 - 7
This register contains the lower byte bits (0-7) of the measured signal quality of bit sync amplitude used for drop lock deci-
sions. This register combined with the lower byte represents a 16-bit value, representing the measured signal quality for the
bit sync amplitude. This measurement is made every 128 symbols.
CONFIGURATION REGISTER 30 ADDRESS (78h) RX SIGNAL QUALITY 2 ACQ THRESHOLD (HIGH)
Bits 0 - 7
This control register contains the upper byte bits (8-15) of the carrier phase variance threshold used for acquisition. This
register combined with the lower byte represents a 16-bit threshold value for carrier phase variance measurement made
during acquisition at each antenna dwell and is based on the choice of the best antenna. This threshold is used with the bit
sync threshold in registers 22 and 23 to declare acquisition. A higher value in this threshold will increase the probability of
acquisition and false alarm.
CONFIGURATION REGISTER 31 ADDRESS (7Ch) RX SIGNAL QUALITY 2 ACQ THRESHOLD (LOW)
Bits 0 - 7
This control register contains the lower byte bits (0-7) of the carrier phase variance threshold used for acquisition.
CONFIGURATION REGISTER 32 ADDRESS (80h) RX SIGNAL QUALITY 2 ACQ READ (HIGH)
Bits 0 - 7
This status register contains the upper byte bits (8-15) of the measured signal quality of the carrier phase variance used for
acquisition. This register combined with the lower byte generates a 16-bit value, representing the measured signal quality
of the carrier phase variance. This measurement is made during acquisition at each antenna dwell and is based on the se-
lected best antenna.
CONFIGURATION REGISTER 33 ADDRESS (84h) RX SIGNAL QUALITY 2 ACQ READ (LOW)
Bits 0 - 7
This status register contains the lower byte bits (0-7) of the measured signal quality of the carrier phase variance used for
acquisition. This register combined with the lower byte generates a 16-bit value, representing the measured signal quality
of the carrier phase variance. This measurement is made during acquisition at each antenna dwell and is based on the se-
lected best antenna.
CONFIGURATION REGISTER 34 ADDRESS (88h) RX SIGNAL QUALITY 2 DATA THRESHOLD (HIGH)
Bits 0-7
This control register contains the upper byte bits (8-15) of the carrier phase variance threshold. This register combined with
the lower byte represents a 16-bit threshold value for the carrier phase variance signal quality measurements made every
128 symbols.
CONFIGURATION REGISTER 35 ADDRESS (8Ch) RX SIGNAL QUALITY 2 DATA THRESHOLD (LOW)
Bits 0-7
This control register contains the lower byte bits (0-7) of the carrier phase variance threshold. This register combined with
the upper byte) represents a 16-bit threshold value for the carrier phase variance signal quality measurements made every
128 symbols.
CONFIGURATION REGISTER 36 ADDRESS (90h) RX SIGNAL QUALITY 2 DATA READ (HIGH)
Bits 0-7
This status register contains the upper byte bits (8-15) of the measured signal quality of the carrier phase variance. This
register combined with the lower byte represents a 16-bit value, of the measured carrier phase variance. This measurement
is made every 128 symbols.
HFA3824A
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