參數(shù)資料
型號(hào)： HFA3824A
廠商： Intersil Corporation
元件分類： 基帶處理器
英文描述： Direct Sequence Spread Spectrum Baseband Processor
中文描述： 直接序列擴(kuò)頻基帶處理器
文件頁(yè)數(shù)： 20/40頁(yè)
文件大?。?/td> 271K
代理商： HFA3824A
2-118
ulation mode. The bit sync amplitude measurement repre-
sents the peak of the correlation out of the PN correlator.
Figure 16 shows the correlation process. The signal is sam-
pled at twice the chip rate (i.e., 22 MSPS). The one sample
that falls closest to the peak is used for a bit sync amplitude
sample for each symbol. This sample is called the on-time
sample. High bit sync amplitude means a good signal. The
early and late samples are the two adjacent samples and
are used for tracking.
The other signal quality measurement is based on phase
noise and that is taken by sampling the correlator output at the
correlator peaks. The phase changes due to scrambling are
removed by differential demodulation during initial acquisition.
Then the phase, the phase rate and the phase variance are
measured and integrated for 16 symbols. The phase variance
is used for the phase noise signal quality measure. Low phase
noise means a stronger received signal.
Procedure to Set Acq. Signal Quality Parameters
(Example)
There are four registers that set the acquisition signal quality
thresholds,
they
are:
CR
(RX_SQX_IN_ACQ). Each threshold consists of two bytes,
high and low that hold a 16-bit number.
These two thresholds, bit sync amplitude CR (22 and 23)
and phase error CR (30 and 31) are used to determine if the
22,
23,
30,
and
31
desired signal is present. If the thresholds are set too “l(fā)ow”,
there is the probability of missing a high signal to noise
detection due to processing a false alarm. If they are set too
“high”, there is the probability of missing a low signal to noise
detection. For the bit sync amplitude, “high” actually means
high amplitude while for phase noise “high” means high SNR
or low noise.
A recommended procedure is to set these thresholds
individually optimizing each one of them to the same false
alarm rate with no desired signal present. Only the
background environment should be present, usually additive
gaussian white noise (AGWN). When programming each
threshold, the other threshold is set so that it always
indicates that the signal is present. Set register CR22 to 00h
while trying to determine the value of the phase error signal
quality threshold for registers CR 30 and 31. Set register
CR30 to FFh while trying to determine the value of the Bit
sync amplitude signal quality threshold for registers 22 and
23. Monitor the Carrier Sense (CRS) output (TEST 7, pin 46)
and adjust the threshold to produce the desired rate of false
detections. CRS indicates valid initial PN acquisition. After
both thresholds are programmed in the device the CRS rate
is a logic “and” of both signal qualities rate of occurrence
over their respective thresholds and will therefore be much
lower than either.
16 SYMBOLS
B
126 SYMBOL SYNC
SFD
JUST
MISSED
DET
ANT1
SYMB
TIMING
DETECT
ANT1
CHECK
ANT2
TX
POWER
RAMP
NO
SIG
FOUND
ANT2
16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS
A
B
A
7S
16 SYMBOLS
B
B
A
B
DETECT
ANT1
SFD DET
START DATA
SEED
DESCRAMBLER
7S
CHECK
ANT2
INTERNAL
SET UP TIME
VERIFY
ANT1
2
NOTES:
4. Worst Case Timing; antenna dwell starts before signal is full strength.
5. Time line shown assumes that antenna 2 gets insufficient signal.
FIGURE 14. DUAL ANTENNA ACQUISITION TIMELINE
2
16 SYMBOLS
78 SYMBOL SYNC
SFD
JUST
MISSED
DET
DETECT
TX
POWER
RAMP
16 SYMBOLS
16 SYMBOLS
16 SYMBOLS
7 SYM
16 SYMBOLS
SYMB
TIMING
VERIFY
SFD DET
START DATA
SEED
DESCRAMBLER
7 SYM
INTERNAL
SET UP TIME
FIGURE 15. SINGLE ANTENNA ACQUISITION TIMELINE
HFA3824A
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