參數資料
型號： HFA3824A
廠商： Intersil Corporation
元件分類： 基帶處理器
英文描述： Direct Sequence Spread Spectrum Baseband Processor
中文描述： 直接序列擴頻基帶處理器
文件頁數： 15/40頁
文件大?。?/td> 271K
代理商： HFA3824A
2-113
Header/Packet Description
The HFA3824A is designed to handle continuous or pack-
etized Direct Sequence Spread Spectrum (DSSS) data
transmissions. The HFA3824A can generate its own pream-
ble and header information or it can accept them from an
external source.
When preamble and header are internally generated the
device supports a synchronization preamble up to 256 sym-
bols, and a header that can include up to five fields. The pre-
amble size and all of the fields are programmable. When
internally generated the preamble is all 1’s (before entering
the scrambler). The actual transmitted pattern of the pream-
ble will be randomized by the scrambler if the user chooses
to utilize the data scrambling option.
When the preamble is externally generated the user can
choose any desirable bit pattern. Note though, that if the pre-
amble bits will be processed by the scrambler which will alter
the original pattern unless it is disabled.
The preamble is always transmitted as a DBPSK waveform
with a programmable length of up to 256 symbols long. The
HFA3824A requires at least 126 preamble symbols to acquire
in a dual antenna configuration (diversity), or a minimum of 78
preamble symbols to acquire under a single antenna configu-
ration. The exact number of necessary preamble symbols
should be determined by the system designer, taking into
consideration the noise and interference requirements in con-
junction with the desired probability of detection vs probability
of false alarm for signal acquisition.
The five available fields for the header are:
SFD Field (16 Bits) -
This field carries the ID to establish
the link. This is a mandatory field for the HFA3824A to estab-
lish communications. The HFA3824A will not declare a valid
data packet, even if it PN acquires, unless it detects the spe-
cific SFD. The SFD field is required for both Internal pream-
ble/header
generation
and
generation. The HFA3824A receiver can be programmed to
time out searching for the SFD. The timer starts counting the
moment that initial PN synchronization has been established
from the preamble.
Signal Field (8 Bits) -
This field indicates whether the data
packet that follows the header is modulated as DBPSK or
DQPSK. In mode 3 the HFA3824A receiver looks at the sig-
External
preamble/header
nal field to determine whether it needs to switch from
DBPSK demodulation into DQPSK demodulation at the end
of the always DBPSK preamble and header fields.
Service Field (8 Bits) -
This field can be utilized as required
by the user.
Length Field (16 Bits) -
This field indicates the number of
data bits contained in the data packet. The receiver can be
programmed (CR0 Bit 1) to check the length field in deter-
mining when it needs to de-assert the MD_RDY interface
signal. MD_RDY envelopes the received data packet as it is
being output to the external processor.
CCITT - CRC 16 Field (16 Bits) -
This field includes the 16-
bit CCITT - CRC 16 calculation of the five header fields. This
value is compared with the CCITT - CRC 16 code calculated
at the receiver. The HFA3824A receiver can be programmed
to drop the link upon a CCITT - CRC 16 error or it can be
programmed to ignore the error and to continue with data
demodulation.
The CRC or cyclic Redundancy Check is a CCITT CRC-16
FCS (frame check sequence). It is the ones compliment of
the remainder generated by the modulo 2 division of the pro-
tected bits by the polynomial:
x
16
+ x
12
+ x
5
+ 1
The protected bits are processed in transmit order. All CRC
calculations are made prior to data scrambling. A shift regis-
ter with two taps is used for the calculation. It is preset to all
ones and then the protected fields are shifted through the
register. The output is then complemented and the residual
shifted out MSB first.
When the HFA3824A generates the preamble and header
internally it can be configured into one of four link protocol
modes.
Mode 0 -
In this mode the preamble is programmable up to 256
bits (all 1’s) and the SFD field is the only field utilized for the
header. This mode only supports DBPSK transmissions for the
entire packet (preamble/header and data).
Mode 1 -
In this mode the preamble is programmable up to 256
bits (all 1’s) and the SFD and CCITT - CRC 16 fields are used
for the header. The data that follows the header can be either
DBPSK or DQPSK. The receiver and transmitter must be pro-
grammed to the proper modulation type.
TABLE 7. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz
DATA
MODULATION
ADC SAMPLE
CLOCK
(MHz)
TX SETUP CR 3
BITS 4, 3
RX SET UP CR 2
BITS 4, 3
DATA RATE
FOR 11
CHIPS/BIT
(MBPS)
DATA RATE
FOR 13
CHIPS/BIT
(MBPS)
DATA RATE
FOR 15
CHIPS/BIT
(MBPS)
DATA RATE
FOR 16
CHIPS/BIT
(MBPS)
DQPSK
44
00 (N = 2)
00
4
3.385
2.933
2.75
DQPSK
22
01 (N = 4)
01
2
1.692
1.467
1.375
DQPSK
11
10 (N = 8)
10
1
0.846
0.733
0.688
DQPSK
5.5
11 (N = 16)
11
0. 5
0.423
0.367
0.344
DBPSK
44
00 (N = 2)
00
2
1.692
1.467
1.375
DBPSK
22
01 (N = 4)
01
1
0.846
0.733
0.688
DBPSK
11
10 (N = 8)
10
0.5
0.423
0.367
0.344
DBPSK
5.5
11 (N = 16)
11
0.25
0.212
0.183
0.171
HFA3824A
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