參數(shù)資料
型號(hào)： HD74AC
廠商： Hitachi,Ltd.
英文描述： HD74AC Series Common Information
中文描述： HD74AC系列通用信息
文件頁(yè)數(shù)： 45/52頁(yè)
文件大小： 220K
代理商： HD74AC
Design Considerations
44
5. Design Rules
The set of design rules listed below are recommended to ensure reliable system operation by providing the
optimum power supply connection to the devices. Most designers will recognize these guidelines as those
they have employed with advanced bipolar logic families.
Use multi-layer boards with V
CC
and ground planes, with the device power pins soldered directly to the
planes to insure the lowest power line impedances possible.
Use decoupling capacitors for every device, usually 0.10
μ
F should be adequate. These capacitors
should be located as close to the ground pin as possible.
Avoid sockets or wirewrap boards whenever possible.
Do not connect capacitors from the outputs directly to ground.
5.1 Decoupling Requirements
FACT, as with other high-performance, high-drive logic families, has special decoupling and printed circuit
board layout requirements. Adhering to these requirements will ensure the maximum advantages are
gained with FACT products.
Local high frequency decoupling is required to supply power to the chip when it is transitioning from a low
to a high value. This power is necessary to charge the load capacitance or drive a line impedance. Figure
17 displays various V
CC
and ground layout schemes along with associated impedances.
For most power distribution networks, the typical impedance is between 50 and 100
. This impedance
appears in series with the load impedance and will cause a droop in the V
CC
at the part. This limits the
available voltage swing at the local node, unless some form of decoupling is used.
This drooping of rails will cause the rise and fall times to become elongated. Consider the example
described in figure 18 to calculate the amount of decoupling necessary. This circuit utilizes an
HD74AC240 driving a 100
bus from a point somewhere in the middle.
Being in the middle of the bus, the driver will see two 100
loads in parallel, or an effective impedance of
50
. To switch the line from rail to rail, a drive of 78 mA is needed; more than 624 mA will be required if
all eight lines switch at once. This instantaneous current requirement will generate a voltage across the
impedance of the power lines, causing the actual V
CC
at the chip to droop. This droop limits the voltage
swing available to the driver. The net effect of the voltage droop will lengthen device rise and fall times
and slow system operation. A local decoupling capacitor is required to act as a low impedance supply for
the driver chip during high current conditions. It will maintain the voltage with acceptable limits and keep
rise and fall times to minimum. The necessary values for decoupling capacitors can be calculated with the
formula given in figure 19.
相關(guān)PDF資料
PDF描述
HD74ALVC162244 16-bit Buffer / Driver with 3-state Outputs(帶三態(tài)輸出的16位緩沖器/驅(qū)動(dòng)器)
HD74ALVC162334 16-bit Universal Bus Driver with 3-state Outputs(帶三態(tài)輸出的16位通用總線驅(qū)動(dòng)器)
HD74ALVC16244 16-bit Buffer / Driver with 3-state Outputs(帶三態(tài)輸出的16位緩沖器/驅(qū)動(dòng)器)
HD74ALVC162831 1-bit to 4-bit Address Register / Driver with 3-state Outputs(三態(tài)輸出的1位-4位地址寄存器/驅(qū)動(dòng)器)
HD74ALVC162834A 1-Of-8 Data Selectors/Multiplexers 16-CDIP -55 to 125
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HD74AC00 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:Quad 2-Input NAND Gate
HD74AC00FP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad 2-input NAND Gate
HD74AC00FPEL 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Quad 2-Input NAND Gate
HD74AC00P 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Quad 2-Input NAND Gate
HD74AC00RPEL 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Quad 2-Input NAND Gate
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