參數(shù)資料
型號(hào)： HD74AC
廠商： Hitachi,Ltd.
英文描述： HD74AC Series Common Information
中文描述： HD74AC系列通用信息
文件頁(yè)數(shù)： 39/52頁(yè)
文件大?。?/td> 220K
代理商： HD74AC
Design Considerations
38
3. CMOS Bus Loading
CMOS logic devices have clamp diodes from all inputs and outputs to V
CC
and ground. While these diodes
increase system reliability by damping out undershoot and overshoot noise, they can cause problems if
power is lost.
Figure 10 exemplifies the situation when power is removed. Any input driven above the V
CC
pin will
forward-bias the clamp diode. Current can then flow into the device, and out V
CC
or any output that is high.
Depending upon the system, this current, I
IN
, can be quite high, and may not allow the bus voltage to reach
a valid high state. One possible solution to eliminate this problem is to place a series resistor in the line.
V
CC
Input
Output
I
CC
I
IN
Iout
Figure 10 Clamp Diode Operation
4. Noise Effects
FACT offers the best noise immunity of any competing technology available today. With input thresholds
specified at 30% and 70% of V
CC
and outputs that drive to within 100 mV of the rails, FACT devices offer
noise margins approaching 30% of V
CC
. At 5 V V
CC
, FACT’s specified input and output levels give almost
1.5 V of noise margin for both ground and V
CC
-born noise. With realistic input thresholds closer to 50% of
V
CC
, the actual margins approach 2.5 V.
However, even the most advanced technology cannot alone eliminate noise problems. Good circuit board
layout techniques are essential to take full advantage of the superior performance of FACT circuits.
Well-designed circuit boards also help eliminate manufacturing and testing problems.
Another recommended practice is to segment the board into a high-speed area, a medium-speed area and a
low-speed area. The circuit areas with high current requirements (i.e., buffer circuits and high-speed logic)
should be as close to the power supplies as possible; low-speed circuit areas can be furthest away.
Decoupling capacitors should be adjacent to all buffer chips; they should be distributed throughout the
logic: one capacitor per ship. Transmission lines need to be terminated to keep reflections minimal. To
minimize crosstalk, long signal lines should not be close together.
相關(guān)PDF資料
PDF描述
HD74ALVC162244 16-bit Buffer / Driver with 3-state Outputs(帶三態(tài)輸出的16位緩沖器/驅(qū)動(dòng)器)
HD74ALVC162334 16-bit Universal Bus Driver with 3-state Outputs(帶三態(tài)輸出的16位通用總線驅(qū)動(dòng)器)
HD74ALVC16244 16-bit Buffer / Driver with 3-state Outputs(帶三態(tài)輸出的16位緩沖器/驅(qū)動(dòng)器)
HD74ALVC162831 1-bit to 4-bit Address Register / Driver with 3-state Outputs(三態(tài)輸出的1位-4位地址寄存器/驅(qū)動(dòng)器)
HD74ALVC162834A 1-Of-8 Data Selectors/Multiplexers 16-CDIP -55 to 125
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HD74AC00 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:Quad 2-Input NAND Gate
HD74AC00FP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad 2-input NAND Gate
HD74AC00FPEL 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Quad 2-Input NAND Gate
HD74AC00P 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Quad 2-Input NAND Gate
HD74AC00RPEL 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Quad 2-Input NAND Gate
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