490
(7) Design a current margin into the programming voltage (V
PP
) power supply.
Ensure that
V
PP
will not depart from 12.0 ±0.6 V (11.4 V to 12.6 V) during programming or erasing.
Programming and erasing may become impossible outside this range.
(8) Ensure that peak overshoot does not exceed the rated value at the FV
PP
and MD
1
pins.
Connect decoupling capacitors as close to the FV
PP
and MD
1
pins as possible.
Also connect decoupling capacitors to the MD
1
pin in the same way when boot mode is uesd.
0.01
μ
F
1.0
μ
F
12 V
FV
PP
H8/3337YF
Figure 20.21 V
PP
Power Supply Circuit Design (Example)
(9) Use the recommended algorithms for programming and erasing flash memory.
These
algorithms are designed to program and erase without subjecting the device to voltage stress and
without sacrificing the reliability of programmed data.
Before setting the program (P) or erase (E) bit in the flash memory control register (FLMCR), set
the watchdog timer to ensure that the P or E bit does not remain set for more than the specified
time.
(10) For details on interrupt handling while flash memory is being programmed or erased,
see the notes on NMI interrupt handling in section 20.4.9, Interrupt Handling during Flash
Memory Programming and Erasing.
(11) Cautions on Accessing Flash Memory Control Registers
1. Flash memory control register access state in each operating mode
The H8/3337YF has flash memory control registers located at addresses H'FF80 (FLMCR),
H'FF82 (EBR1), and H'FF83 (EBR2). These registers can only be accessed when 12 V is
applied to the flash memory program power supply pin, FV
PP
.
Table 1 shows the area accessed for the above addresses in each mode, when 12 V is and is not
applied to FV
PP
.