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Rev. 4.00 Jan 26, 2006 page ix of xxii
Section 5 Interrupt Controller .......................................................................................... 91
5.1
Overview...........................................................................................................................
91
5.1.1
Features................................................................................................................
91
5.1.2
Block Diagram .....................................................................................................
92
5.1.3
Pin Configuration.................................................................................................
93
5.1.4
Register Configuration.........................................................................................
93
5.2
Register Descriptions ........................................................................................................94
5.2.1
System Control Register (SYSCR) ......................................................................
94
5.2.2
Interrupt Priority Registers A and B (IPRA, IPRB).............................................
95
5.2.3
IRQ Status Register (ISR).................................................................................... 102
5.2.4
IRQ Enable Register (IER) .................................................................................. 103
5.2.5
IRQ Sense Control Register (ISCR) .................................................................... 104
5.3
Interrupt Sources ............................................................................................................... 105
5.3.1
External Interrupts ............................................................................................... 105
5.3.2
Internal Interrupts................................................................................................. 106
5.3.3
Interrupt Vector Table.......................................................................................... 106
5.4
Interrupt Operation............................................................................................................ 110
5.4.1
Interrupt Handling Process................................................................................... 110
5.4.2
Interrupt Sequence ............................................................................................... 115
5.4.3
Interrupt Response Time...................................................................................... 116
5.5
Usage Notes ...................................................................................................................... 117
5.5.1
Contention between Interrupt and Interrupt-Disabling Instruction ...................... 117
5.5.2
Instructions that Inhibit Interrupts........................................................................ 118
5.5.3
Interrupts during EEPMOV Instruction Execution .............................................. 118
Section 6 Bus Controller ................................................................................................... 119
6.1
Overview........................................................................................................................... 119
6.1.1
Features................................................................................................................ 119
6.1.2
Block Diagram ..................................................................................................... 121
6.1.3
Pin Configuration................................................................................................. 122
6.1.4
Register Configuration......................................................................................... 123
6.2
Register Descriptions ........................................................................................................ 124
6.2.1
Bus Width Control Register (ABWCR)............................................................... 124
6.2.2
Access State Control Register (ASTCR) ............................................................. 125
6.2.3
Wait Control Registers H and L (WCRH, WCRL).............................................. 125
6.2.4
Bus Release Control Register (BRCR) ................................................................ 130
6.2.5
Bus Control Register (BCR) ................................................................................ 132
6.2.6
Chip Select Control Register (CSCR).................................................................. 134
6.2.7
DRAM Control Register A (DRCRA) ................................................................. 135
6.2.8
DRAM Control Register B (DRCRB) ................................................................. 137
6.2.9
Refresh Timer Control/Status Register (RTMCSR) ............................................ 140