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型號(hào)：	HD6433066F
元件分類：	微控制器/微處理器
英文描述：	32-BIT, MROM, MICROCONTROLLER, PQFP100
封裝：	QFP-100
文件頁(yè)數(shù)：	507/751頁(yè)
文件大?。?/td>	5077K
代理商：	HD6433066F

Section 13 Serial Communication Interface

Rev. 4.00 Jan 26, 2006 page 533 of 938

REJ09B0276-0400

Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 13.20 shows a

sample flowchart for transmitting and receiving serial data simultaneously and indicates the

procedure to follow.

Read receive data from RDR, and

clear RDRF flag to 0 in SSR

Start of transmitting and receiving

Error handling

Read ORER flag in SSR

Read RDRF flag in SSR

Read TDRE flag in SSR

Write transmit data in TDR and

clear TDRE flag to 0 in SSR

End of transmitting

and receiving?

Clear TE and RE bits to 0 in SCR

SCI initialization: the transmit data output function of the

TxD pin and the read data input function of the RxD pin

are selected, enabling simultaneous transmitting and

SCI status check and transmit data write: read SSR, check

that the TDRE flag is 1, then write transmit data in TDR

and clear the TDRE flag to 0.

Notification that the TDRE flag has changed from 0 to 1

can also be given by the TXI interrupt.

Receive error handling: if a receive error occurs, read the

ORER flag in SSR, then after executing the necessary

error handling, clear the ORER flag to 0.

Neither transmitting nor receiving can resume while the

ORER flag remains set to 1.

SCI status check and receive data read: read SSR, check

that the RDRF flag is 1, then read receive data from RDR

and clear the RDRF flag to 0. Notification that the RDRF

flag has changed from 0 to 1 can also be given by the RXI

To continue transmitting and receiving serial data: check

the RDRF flag, read RDR, and clear the RDRF flag to 0

before the MSB (bit 7) of the current frame is received.

Also check that the TDRE flag is set to 1, indicating that

data can be written, write data in TDR, then clear the

TDRE flag to 0 before the MSB (bit 7) of the current frame

is transmitted. When the DMAC is activated by a transmit-

data-empty interrupt request (TXI) to write data in TDR,

the TDRE flag is checked and cleared automatically.

When the DMAC is activated by a receive-data-full

interrupt request (RXI) to read RDR, the RDRF flag is

cleared automatically.

Note: When switching from transmitting or receiving to simultaneous transmitting and receiving, clear both the TE bit

and the RE bit to 0, then set both bits to 1 simultaneously.

Figure 13.20 Sample Flowchart for Simultaneous Serial Transmitting and Receiving

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