
Section 18 ROM
Rev. 4.00 Jan 26, 2006 page 639 of 938
REJ09B0276-0400
18.6.2
Software Protection
Software protection can be implemented by setting the RAMS bit in RAM control register
(RAMCR) and erase block register (EBR). When software protection is in effect, setting the P or E
bit in flash memory control register (FLMCR) does not cause a transition to program mode or
erase mode. (See table 18.9.)
Table 18.9
Software Protection
Function
Item
Description
Program Erase
Verify*
1
Emulation
protection*
2
Setting the RAMS bit in RAMCR sets the
program/erase-protected state for all
blocks.
No*
2
No*
3
Yes
Block
specification
protection
Erase protection can be set for individual
blocks by settings in erase block register
(EBR).*
4
However, program protection is disabled.
Setting EBR to H'00 places all blocks in
the erase-protected state.
—
No
Yes
Notes: 1. Two modes: program-verify mode and erase-verify mode.
2. Programming to the RAM area that overlaps flash memory is possible.
3. All blocks become unerasable, and specification by block is impossible.
4. Set H'00 in the EBR bits, except for erase.
18.6.3
Error Protection
In error protection, an error is detected when this LSI runaway occurs during flash memory
programming/erasing*
1, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the LSI malfunctions during flash memory programming/erasing, the FLER bit*
2 is set to 1 in
flash memory status register (FLMSR) and the error protection state is entered. The FLMCR and
EBR settings*
3 are retained, but program mode or erase mode is aborted at the point at which the
error occurred. When 1 is set in the FLER bit, transition to the program mode or erase mode
cannot be made even by setting the P and E bits in FLMCR. However, PV and EV bit in FLMCR
setting is enabled, and a transition can be made to verify mode.