參數(shù)資料
型號(hào)： HD49235FS
廠商： Hitachi,Ltd.
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processor for CD
中文描述： 數(shù)字信號(hào)處理器的CD
文件頁(yè)數(shù)： 30/41頁(yè)
文件大?。?/td> 192K
代理商： HD49235FS
HD49235FS
Rev.2, Aug. 1995, page 30 of 41
CLV Servo Control
Compact discs (CDs) are recorded at a constant linear velocity (CLV). This block performs CLV motor
control.
MSTOP:
This CLV phase error output pin either is in the high-impedance state, or outputs a constant
low signal, a constant high signal, or a pulse-width modulated waveform with a duty cycle of 0 to
100%, depending on the CLV operating mode.
PWM:
This CLV velocity error output pin either is in the high-impedance state, outputs a constant low
signal, outputs a constant high signal, or outputs a pulse-width modulated waveform with a duty cycle
of 0 to 100%, depending on the CLV operating mode.
MON:
This output signal indicates when the disc motor is on. When the disc motor is on, this pin is at
the high level, except in stop mode.
PW64:
This pin outputs the brake release signal.
ROTD:
This pin can be used to monitor the most significant bit of the 7-bit (128-step) output at the
PWM pin.
CLVS:
This output pin differentiates between the starting and normal CLV modes. High output
indicates normal mode.
Next the operating modes will be described. Table 2 indicates the CLV control output states in each
mode.
Table 2
CLV Control Output
Outputs Signals
CLV Mode
ED3 to 0
MON
MSTOP (Phase Error)
PWM (Speed Error)
STOP
0000
L
Z
Z
PLAY
0110
H
50% (starting mode)
0 to 100% (normal mode)
0 to 100%
ROT
1000
H
50%
H
KICK
1001
H
50%
Set by microprocessor
BRAKE
1010
H
50%
L
ACS
1100
H
50%
0 to 100%
START
1110
H
50%
0 to 100%
NORM
1111
H
0 to 100%
0 to 100%
1. Stop Mode
This is the state in which the motor is stopped. The free-running frequency of the data strobe VCO is
automatically adjusted in this mode.
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