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參數(shù)資料
| 型號： | HD49235FS |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processor for CD |
| 中文描述： | 數(shù)字信號處理器的CD |
| 文件頁數(shù)： | 13/41頁 |
| 文件大?。?/td> | 192K |
| 代理商： | HD49235FS |
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HD49235FS
Rev.2, Aug. 1995, page 13 of 41
AMPP:
Non-inverting input to the amplifier.
This chip uses a PLL for recovery of the bit clock. A built-in circuit automatically adjusts the free-
running frequency of the PLL, so fewer adjustments are required on the production line. The chip can
be forced to adjust its own free-running frequency whenever power is turned on or the speed is changed
by switching to CLV stop mode. Thus the free-running frequency is always set to the center of the lock
frequency range even if changes occur in the VCO and external circuit constants due to aging.
The principle and usage of automatic adjustment of the free-running frequency will be described below.
a. In automatic adjustment of the VCO free-running frequency, this chip uses the disc stop signal. The
disc stop signal is turned on when the microprocessor writes 0000 in bits ED3, ED2, ED1, and ED0
of register E in the chip’s microprocessor interface. (See section 6, Microprocessor Interface.)
b. When the disc stop signal is turned on, counter (A) in figure 2 becomes a divide-by-98 counter,
switch (A) is connected to the output from the VCO, and switch (B) is connected to digital 0.
At this time, the circuit for the PDOUT1 output is stopped, so the output of the LPF1 connected to
PDOUT1 goes to the fixed DC bias level, which is 1/2 V
DD
.
The loop formed by PDOUT2
→
LPF2
→
amplifier
→
VCO
→
counter (A) now operates to lock
the VCO oscillator frequency to 34.5744 MHz, which is 8 times the standard CD bit rate (4.3218
MHz).
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