參數(shù)資料
型號(hào)： HCD40C4344R
廠商： Hitachi,Ltd.
英文描述： 4-bit HMCS400-series microcomputer(4位單片微計(jì)算機(jī))
中文描述： 4位HMCS400系列微電腦（4位單片微計(jì)算機(jī)）
文件頁(yè)數(shù)： 16/100頁(yè)
文件大?。?/td> 610K
代理商： HCD40C4344R
HD404344R Series/HD404394 Series
16
RAM Memory Map
The MCU RAM contains 256 digits
×
4 bits which is used for the memory registers, and the data and stack
areas. The interrupt control bits area, special register area, and the register flag area are mapped into the
RAM memory. The RAM memory area is shown in figure 2 and explained as follows.
A/D channel register (ACR)
A/D data register lower (ADRL)
A/D data register upper (ADRU)
A/D mode register 1 (AMR1)
A/D mode register 2 (AMR2)
$000
$000
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$040
$050
$033
$00A
$00B
$00E
$00F
W
W
R/W
R/W
W
R/W
R/W
W
W
R/W
R/W
W
W
W
W
W
W
W
W
R
R
R
R
$3C0
RAM-mapped registers
Memory registers (MR)
Stack (64 digits)
Interrupt control bits area
Port mode register A (PMRA)
Serial mode register (SMR)
Serial data register lower (SRL)
Serial data register upper (SRU)
Not used
Timer mode register B1 (TMB1)
Timer B (TRBL/TWBL)
(TRBU/TWBU)
Miscellaneous register (MIS)
Timer mode register C (TMC)
Timer C (TRCL/TWCL)
(TRCU/TWCU)
Register flag area
Port R0 DCR (DCR0)
Port R1 DCR (DCR1)
Port R2 DCR (DCR2)
Port R3 DCR (DCR3)
Not used
*
Two registers are mapped
on the same area ($00A,
$00B, $00E, $00F).
Timer read register B lower (TRBL)
Timer read register B upper (TRBU)
Timer read register C lower (TRCL)
Timer read register C upper (TRCU)
Timer write register B lower (TWBL)
Timer write register B upper (TWBU)
Timer write register C lower (TWCL)
Timer write register C upper (TWCU)
R: Read only
W: Write only
R/W: Read/write
Note:
$016
$017
$018
$019
$01A
R
R
W
W
$3FF
W
W
W
W
Port mode register B (PMRB)
Port mode register C (PMRC)
Timer mode register B2 (TMB2)
Not used
$030
$031
$032
Data (176 digits)
Not used
Not used
*
$03F
Not used
$100
W
Port D
4
, D
5
DCR
W
Port D
0
–D
3
DCR
$020
$023
$024
$025
$026
$02D
$02C
Not used
(DCD0)
(DCD1)
Figure 2 RAM Memory Map
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