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參數(shù)資料
| 型號： | HB52D88GB-F |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64 MB Unbuffered SDRAM Micro DIMM(64 MB 未緩沖同步DRAM DIMM) |
| 中文描述： | 64兆微型無緩沖SDRAM的內(nèi)存（64 MB的未緩沖同步的DRAM內(nèi)存） |
| 文件頁數(shù)： | 6/23頁 |
| 文件大?。?/td> | 94K |
| 代理商： | HB52D88GB-F |
HB52D88GB-F
6
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
23
SDRAM cycle time
(2nd highest
CE
latency)
(-A6F/A6FL) 10 ns
1
0
1
0
0
0
0
0
A0
CL=2
(-B6F/B6FL) 15 ns
1
1
1
1
0
0
0
0
F0
24
SDRAM access from Clock
(2nd highest
CE
latency)
(-A6F/A6FL) 6 ns
0
1
1
0
0
0
0
0
60
CL=2
(-B6F/B6FL) 8 ns
1
0
0
0
0
0
0
0
80
25
SDRAM cycle time
(3rd highest
CE
latency)
Undefined
0
0
0
0
0
0
0
0
00
26
SDRAM access from Clock
(3rd highest
CE
latency)
Undefined
0
0
0
0
0
0
0
0
00
27
Minimum row precharge time
0
0
0
1
0
1
0
0
14
20 ns
28
Row active to row active min
RE
to
CE
delay min
Minimum
RE
pulse width
0
0
0
1
0
1
0
0
14
20 ns
29
0
0
0
1
0
1
0
0
14
20 ns
30
0
0
1
1
0
0
1
0
32
50 ns
31
Density of each bank on
module
0
0
0
1
0
0
0
0
10
64M byte
32
Address and command signal
input setup time
0
0
1
0
0
0
0
0
20
2 ns
33
Address and command signal
input hold time
0
0
0
1
0
0
0
0
10
1 ns
34
Data signal input setup time
0
0
1
0
0
0
0
0
20
2 ns
35
Data signal input hold time
0
0
0
1
0
0
0
0
10
1 ns
36 to 61 Superset information
0
0
0
0
0
0
0
0
00
Future use
62
SPD data revision code
0
0
0
1
0
0
1
0
12
Rev. 1.2A
63
Checksum for bytes 0 to 62
(-A6F/A6FL)
0
0
0
0
1
1
0
1
0D
13
(-B6F/B6FL)
0
1
1
1
1
1
0
1
7D
125
64
Manuf ac urer’ s JEDEC ID c ode
0
0
0
0
0
1
1
1
07
HITACHI
65 to 71 Manuf ac urer’ s JEDEC ID c ode
0
0
0
0
0
0
0
0
00
72
Manufacturing location
×
×
×
×
×
×
×
×
××
*
3
(ASCII-
8bit code)
73
Manufacturer’s part number
0
1
0
0
1
0
0
0
48
H
74
Manufacturer’s part number
0
1
0
0
0
0
1
0
42
B
75
Manufacturer’s part number
0
0
1
1
0
1
0
1
35
5
76
Manufacturer’s part number
0
0
1
1
0
0
1
0
32
2
77
Manufacturer’s part number
0
1
0
0
0
1
0
0
44
D
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