HB28E016/D032/D064/B128MM2
68
Clearing Status Bits
As described in the previous paragraphs, in SPI mode, status bits are reported to the host in three different
formats: response R1, response R2 and data error token (the same bits may exist in multiple response
types— e.g Card ECC failed).
As in the MultiMediaCard mode, error bits are cleared when read by the host, regardless of the response
format. State indicators are either cleared by reading or in accordance with the card state. All Error/Status
bits defined in MultiMediaCard mode, with the exception of underrun and overrun, have the same meaning
and usage in SPI mode. The following table summarizes the set and clear conditions for the various status
bits:
Type:
E: Error bit.
S: Status bit.
R: Detected and set for the actual command response.
X: Detected and set during command execution. The host must poll the card by sending status
command in order to read these bits.
Clear Condition:
A: According to the card state.
C: Clear by read.
SPI mode Status bits
Identifier
ncluded
in resp
Type
Value
Description
Clear
condition
Out of range
R2
DataErr
E R X
’
0
’
= no error
’
1
’
= error
The command argument was out of
allowed range for these Hitachi
MultiMediaCards.
C
Address error
R1 R2
E R X
’
0
’
= no error
’
1
’
= error
An address which did not match the
block length was used in the
command.
C
Erase sequence
error
R1 R2
E R
’
0
’
= no error
’
1
’
= error
An error in the sequence of erase
command sequence.
C
Error param
R2
E X
’
0
’
= no error
’
1
’
= error
An error in the parameters of the
erase command sequence.
C
Parameter error
R1 R2
E R X
’
0
’
= no error
’
1
’
= error
An error in the parameters of the
command.
C
WP violation
R2
E R X
’
0
’
= not protected
’
1
’
= protected
Attempt to program a write protected
block.
C
Com CRC error
R1 R2
E R
’
0
’
= no error
’
1
’
= error
The CRC check of the previous
command failed.
C