參數(shù)資料
型號(hào): GS881Z32CGD-150IVT
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 256K X 32 ZBT SRAM, 7.5 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁數(shù): 37/37頁
文件大?。?/td> 1239K
代理商: GS881Z32CGD-150IVT
GS881Z18/32/36CD 165-Bump BGA Pin Description
Symbol
Type
Description
A0, A1
I
Address field LSBs and Address Counter Preset Inputs
A
I
Address Inputs
BA
In
Byte Write signal for data inputs DQA; active low
BB
In
Byte Write signal for data inputs DQB; active low
BC
In
Byte Write signal for data inputs DQC; active low
BD
In
Byte Write signal for data inputs DQD; active low
NC
No Connect
CK
I
Clock Input Signal; active high
CKE
I
Clock Enable; active low
W
I
Write Enable; active low
E1
I
Chip Enable; active low
E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
G
I
Output Enable; active low
DQA
I/O
Byte A Data Input and Output pins
DQB
I/O
Byte B Data Input and Output pins
DQC
I/O
Byte C Data Input and Output pins
DQD
I/O
Byte D Data Input and Output pins
DQPA
I/O
9th Data I/O Pin; Byte A
DQPB
I/O
9th Data I/O Pin; Byte B
DQPC
I/O
9th Data I/O Pin; Byte C
DQPD
I/O
9th Data I/O Pin; Byte D
ADV
I
Burst address counter advance enable; active high
ZZ
I
Sleep mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
TMS
I
Scan Test Mode Select
TDI
I
Scan Test Data In
TDO
O
Scan Test Data Out
TCK
I
Scan Test Clock
MCH
Must Connect High
DNU
Do Not Use
VDD
I
Core power supply
VSS
I
I/O and Core Ground
VDDQ
I
Output driver power supply
GS881Z18/32/36C(T/D)-xxxV
Rev: 1.00a 10/2009
9/37
2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
相關(guān)PDF資料
PDF描述
GS881Z32CGD-150VT 256K X 32 ZBT SRAM, 7.5 ns, PBGA165
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