參數(shù)資料
型號(hào)： GS881Z32CGD-150VT
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 256K X 32 ZBT SRAM, 7.5 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù)： 1/37頁(yè)
文件大?。?/td> 1239K
代理商： GS881Z32CGD-150VT
GS881Z18/32/36C(T/D)-xxxV
9Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–150 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.00a 10/2009
1/37
2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
User-configurable Pipeline and Flow Through mode
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
Fully pin-compatible with both pipelined and flow through
NtRAM, NoBL and ZBT SRAMs
IEEE 1149.1 JTAG-compatible Boundary Scan
1.8 V or 2.5 V core power supply
1.8 V or 2.5 V I/O supply
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2M, 4M, and 18M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ pin for automatic power-down
JEDEC-standard packages
RoHS-compliant 100-lead TQFP and 165-bump BGA
packages available
Functional Description
The GS881Z18/32/36C(T/D)-xxxV is a 9Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS881Z18/32/36C(T/D)-xxxV may be configured by the
user to operate in Pipeline or Flow Through mode. Operating
as a pipelined synchronous device, in addition to the rising-
edge-triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS881Z18/32/36C(T/D)-xxxV is implemented with GSI's
high performance CMOS technology and is available in
JEDEC-standard 100-pin TQFP and 165-bump BGA packages.
Paramter Synopsis
-250
-200
-150
Unit
Pipeline
3-1-1-1
tKQ
tCycle
3.0
4.0
3.0
5.0
3.8
6.7
ns
Curr (x18)
Curr (x32/x36)
200
230
170
195
140
160
mA
Flow Through
2-1-1-1
tKQ
tCycle
5.5
6.5
7.5
ns
Curr (x18)
Curr (x32/x36)
160
185
140
160
128
145
mA
相關(guān)PDF資料
PDF描述
GS881Z36BGT-200T 256K X 36 ZBT SRAM, 6.5 ns, PQFP100
GS881Z36BGT-250IT 256K X 36 ZBT SRAM, 5.5 ns, PQFP100
GS88218AB-133 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS88218AB-133I 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS88218AB-150 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
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參數(shù)描述
GS881Z36AT-133 制造商:GSI 制造商全稱:GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS881Z36AT-133I 制造商:GSI 制造商全稱:GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS881Z36AT-150 制造商:GSI 制造商全稱:GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS881Z36AT-150I 制造商:GSI 制造商全稱:GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS881Z36AT-166 制造商:GSI 制造商全稱:GSI Technology 功能描述:9Mb Pipelined and Flow Through Synchronous NBT SRAM
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