參數(shù)資料
型號(hào): GS881Z32CGD-150VT
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 256K X 32 ZBT SRAM, 7.5 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù): 24/37頁(yè)
文件大小: 1239K
代理商: GS881Z32CGD-150VT
GS881Z18/32/36C(T/D)-xxxV
Rev: 1.00a 10/2009
30/37
2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
JTAG Port Recommended Operating Conditions and DC Characteristics (1.8/2.5 V Version)
Parameter
Symbol
Min.
Max.
Unit Notes
1.8 V Test Port Input Low Voltage
VILJ1
–0.3
0.3 * VDD1
V
1
2.5 V Test Port Input Low Voltage
VILJ2
–0.3
0.3 * VDD2
V
1
1.8 V Test Port Input High Voltage
VIHJ1
0.6 * VDD1
VDD1 +0.3
V
1
2.5 V Test Port Input High Voltage
VIHJ2
0.6 * VDD2
VDD2 +0.3
V
1
TMS, TCK and TDI Input Leakage Current
IINHJ
–300
1
uA
2
TMS, TCK and TDI Input Leakage Current
IINLJ
–1
100
uA
3
TDO Output Leakage Current
IOLJ
–1
1
uA
4
Test Port Output High Voltage
VOHJ
1.7
V
5, 6
Test Port Output Low Voltage
VOLJ
0.4
V
5, 7
Test Port Output CMOS High
VOHJC
VDDQ – 100 mV
V
5, 8
Test Port Output CMOS Low
VOLJC
100 mV
V
5, 9
Notes:
1. Input Under/overshoot voltage must be –2 V < Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ VIN VDDn
3. 0 V
VIN VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOLJC = +100 uA
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDDQ/2
Output reference level
VDDQ/2
DQ
VDDQ/2
50
30pF*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
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