參數(shù)資料
型號(hào): GS88136CD-333IT
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 256K X 36 CACHE SRAM, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, FPBGA-165
文件頁數(shù): 11/37頁
文件大?。?/td> 1286K
代理商: GS88136CD-333IT
AC Electrical Characteristics
Parameter
Symbol
-333
-300
-250
-200
-150
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Pipeline
Clock Cycle Time
tKC
3.0
3.3
4.0
5.0
6.7
ns
Clock to Output Valid
tKQ
2.5
2.5
2.5
3.0
3.8
ns
Clock to Output Invalid
tKQX
1.5
1.5
1.5
1.5
1.5
ns
Clock to Output in Low-Z
tLZ1
1.5
1.5
1.5
1.5
1.5
ns
Setup time
tS
1.0
1.0
1.2
1.4
1.5
ns
Hold time
tH
0.1
0.1
0.2
0.4
0.5
ns
Flow
Through
Clock Cycle Time
tKC
4.5
5.0
5.5
6.5
7.5
ns
Clock to Output Valid
tKQ
4.5
5.0
5.5
6.5
7.5
ns
Clock to Output Invalid
tKQX
2.0
2.0
2.0
2.0
2.0
ns
Clock to Output in Low-Z
tLZ1
2.0
2.0
2.0
2.0
2.0
ns
Setup time
tS
1.3
1.4
1.5
1.5
1.5
ns
Hold time
tH
0.3
0.4
0.5
0.5
0.5
ns
Clock HIGH Time
tKH
1.0
1.0
1.3
1.3
1.5
ns
Clock LOW Time
tKL
1.2
1.2
1.5
1.5
1.7
ns
Clock to Output in
High-Z
tHZ1
1.5
2.5
1.5
2.5
1.5
2.5
1.5
3.0
1.5
3.0
ns
G to Output Valid
tOE
2.5
2.5
2.5
3.0
3.8
ns
G to output in Low-Z
tOLZ1
0
0
0
0
0
ns
G to output in High-Z
tOHZ1
2.5
2.5
2.5
3.0
3.8
ns
ZZ setup time
tZZS2
5
5
5
5
5
ns
ZZ hold time
tZZH2
1
1
1
1
1
ns
ZZ recovery
tZZR
20
20
20
20
20
ns
GS88118C(T/D)/GS88132C(T/D)/GS88136C(T/D)
Rev: 1.01 6/2010
19/37
2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
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