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參數(shù)資料
| 型號： | GS880F36 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 8Mb（256K x 36Bit) Synchronous Burst SRAM(8M位（256K x 36位）同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）) |
| 中文描述： | 8MB的（256 × 36Bit）同步突發(fā)靜態(tài)存儲器（800萬位（256K × 36位）同步靜態(tài)隨機(jī)存儲器（帶2位脈沖地址計(jì)數(shù)器）） |
| 文件頁數(shù)： | 1/22頁 |
| 文件大小： | 310K |
| 代理商： | GS880F36 |
Rev: 1.06 9/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
1/22
2000, Giga Semconductor, Inc.
Preliminary
GS880F18/36T-11/11.5/12/14/18
512K x 18, 256K x 36
8Mb Sync Burst SRAMs
11 ns–18 ns
3.3 V V
DD
3.3 V and 2.5 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
Flow Through mode operation
3.3 V +10%/–5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Common data inputs and data outputs
Clock Control, registered, address, data, and control
Internal self-timed write cycle
Automatic power-down for portable applications
100-lead TQFP package
-11
-11.5
Flow
Through
2-1-1-1
I
DD
Functional Description
Applications
The GS880F18/36T is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Designing For Compatibility
The JEDEC Standard for Burst RAMS calls for a FT mode pin
option (pin 14 on TQFP). Board sites for flow through Burst
RAMS should be designed with V
SS
connected to the FT pin
location to ensure the broadest access to multiple vendor
sources. Boards designed with FT pin pads tied low may be
stuffed with GSI’s Pipeline/Flow Through-configurable Burst
RAMS or any vendor’s Flow Through or configurable Burst
SRAM. Bumps designed with the FT pin location tied high or
floating must employ a non-configurable Flow Through Burst
RAM, like this RAM, to achieve flow through functionality.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(high) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS880F18/36T operates on a 3.3 V power supply, and all
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuit.
-12
12 ns
15 ns
180 mA
-14
14 ns
15 ns
175 mA
-18
18 ns
20 ns
165 mA
t
KQ
tCycle
11 ns
15 ns
180 mA
11.5 ns
15 ns
180 mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS880Z18 | 8Mb Pipelined and Flow Through Synchronous NBT SRAM(8M位流水線式和流通型同步NBT靜態(tài)RAM) |
| GS880Z36 | 8Mb Pipelined and Flow Through Synchronous NBT SRAM(8M位流水線式和流通型同步NBT靜態(tài)RAM) |
| GS880Z36AT-133I | 9Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS880Z36AT-150 | 9Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS880Z36AT-150I | 9Mb Pipelined and Flow Through Synchronous NBT SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS880F36AT-5.5 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs |
| GS880F36AT-5.5I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs |
| GS880F36AT-6 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs |
| GS880F36AT-6.5 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs |
| GS880F36AT-6.5I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs |
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