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參數(shù)資料
| 型號： | GS880E18GT-66I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 CACHE SRAM, 18 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 18/25頁 |
| 文件大?。?/td> | 850K |
| 代理商： | GS880E18GT-66I |
Rev: 1.11 11/2000
25/25
2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
GS880E18/32/36TRev1.04h
5/1999;
1.05 9/1999I
Format/Typos
Last Page/Fixed “GSGS..” in Ordering Information Note.
Fromatted Pin Outs and Pin Description to new small caps.
Formatted Block diagrams to new small caps.
Formatted Timing Diagrams to new small caps.
Changed “Flow thru” to “Flow Through” in Timing Diagrams.
Package Diagram/Changed “Dimesion” to “Dimension”.
Content
5/Fixed pin description table to match pinouts.
Pin Description/Changed chip enables to match pins.
Pin Description/Changed pin 80 from NC to Address Input.
Pin Description/Rearranged Address Inputs to match order of
Pinout
Package Diagram/Changed Dimension D Max from 20.1 to
22.1
GS880E18/32/36T1.05 11/
1999K880E18/32/36T1.06 1/
2000L
Content
Changed Flow Through Read-Write Cycle Timing Diagram for
accuracy.
Changed order of TQFP Address Inputs to match pinout.
Changed order of TQFP DATA Input and Output pins to
match pinout.
New GSI Logo.
GS880E18/32/36T1.06 1/
2000L;
GS880E18/32/36T1.07 3/
2000N;
Content
Changed all speed bin information (headings, references,
tables, ordering info..) to reflect 150 - 80Mhz
GS880E18/32/36T1.07 3/
2000N;
GS880E18/32/36T1.08 3/
2000O;
Content
Corrections to AC Electrical Characteristics Table -
GS880E18/32/36T1.08 3/
2000O;
880E183236_r1_09
Content/Format
Removed 150 MHz speed bin
Changed 133 MHz and 117 MHz speed bins to 11 ns and
11.5 ns (100 MHz) numbers
Updated format to comply with Technical Publications
standards
880E18_r1_09;
880E18_r1_10
Content
Updated Capitance table—removed Input row and changed
Output row to I/O
880E18_r1_10;
880E18_r1_11
Content
Corrected typo in AC Electrical Characteristics table
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS880F18T-14T | 512K X 18 CACHE SRAM, 14 ns, PQFP100 |
| GS880Z18AGT-133I | 512K X 18 ZBT SRAM, 8.5 ns, PQFP100 |
| GS88136T-11.5IT | 256K X 36 CACHE SRAM, 11.5 ns, PQFP100 |
| GS881E36BT-150T | 256K X 36 CACHE SRAM, 7.5 ns, PQFP100 |
| GS881E18BD-150 | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS880E18T | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs |
| GS880E18T-100 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs |
| GS880E18T-100I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs |
| GS880E18T-11 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs |
| GS880E18T-11.5 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs |
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