參數(shù)資料
型號(hào)： GS8672Q38BE-500I
廠商： GSI TECHNOLOGY
元件分類(lèi)： SRAM
英文描述： 2M X 36 QDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, FPBGA-165
文件頁(yè)數(shù)： 29/29頁(yè)
文件大?。?/td> 791K
代理商： GS8672Q38BE-500I
Separate I/O SigmaQuad-II+ ECCRAM Read Truth Table
A
R
Output Next State
Q
K
↑
(tn)
K
↑
(tn)
K
↑
(tn)
K
↑
(tn+2)
K
↑
(tn+3)
X
1
Deselect
Hi-Z/0
V
0
Read
Q0
Q1
Notes:
1. X = Don’t Care, 1 = High, 0 = Low, V = Valid.
2. R is evaluated on the rising edge of K.
3. Q0 and Q1 are the first and second data output transfers in a read.
4. Users should not clock in metastable addresses.
5. When On-Die Termination is disabled (ODT = 0), Q drivers are disabled (i.e., Q pins are tri-stated) for one cycle in response to NOP and
Write commands, 2.5 cycles after the command is sampled.
6. When On-Die Termination is enabled (ODT = 1), Q drivers are enabled Low (i.e., Q pins are driven Low) for one cycle in response to
NOP and Write commands, 2.5 cycles after the command is sampled. This is done so that the ASIC/Controller can enable On-Die
Termination on its data inputs without having to cope with the termination pulling tri-stated data inputs to VDDQ/2 (i.e., to the switch point
of the data input receivers).
GS8672Q20/38BE-500/450/400
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 4/2011
9/29
2011, GSI Technology
Preliminary
Separate I/O SigmaQuad-II+ ECCRAM Write Truth Table
A
W
BWn
Input Next State
D
K
↑
(tn + )
K
↑
(tn)
K
↑
(tn)
K
↑
(tn + )
K
↑, K ↑
(tn), (tn + )
K
↑
(tn)
K
↑
(tn + )
V
0
Write Byte Dx0, Write Byte Dx1
D0
D1
V
0
1
Write Byte Dx0, Write Abort Byte Dx1
D0
X
V
0
1
0
Write Abort Byte Dx0, Write Byte Dx1
X
D1
X
0
1
Write Abort Byte Dx0, Write Abort Byte Dx1
X
1
X
Deselect
X
Notes:
1. X = Don’t Care, H = High, L = Low, V = Valid.
2. W is evaluated on the rising edge of K.
3. D0 and D1 are the first and second data input transfers in a write.
4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.).
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