參數(shù)資料
型號(hào)： GS8672Q38BE-500I
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 2M X 36 QDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, FPBGA-165
文件頁(yè)數(shù)： 25/29頁(yè)
文件大?。?/td> 791K
代理商： GS8672Q38BE-500I
GS8672Q20/38BE-500/450/400
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 4/2011
5/29
2011, GSI Technology
Preliminary
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II+ ECCRAM interface and truth table are optimized for alternating reads and writes. Separate
I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers
from Separate I/O ECCRAMs can cut the RAM’s bandwidth in half.
Alternating Read-Write Operations
SigmaQuad-II+ ECCRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted.
- R and W high always deselects the RAM.
- All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for
details.
SigmaQuad-II+ B2 ECCRAM DDR Read
The read port samples the status of the Address Input and R pins at each rising edge of K. A Low on the Read Enable pin, R, begins
a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied High), and
after the following rising edge of K with a rising edge of C (or by K if C and C are tied High). Clocking in a High on the Read
Enable pin, R, begins a read port deselect cycle.
SigmaQuad-II+ B2 ECCRAM DDR Write
The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of
K. A Low on the Write Enable pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is
clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on
the rising edge of K along with the write address. Clocking in a High on W causes a write port deselect cycle.
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