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參數(shù)資料
| 型號： | GS8672Q38BE-500I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 2M X 36 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁數(shù)： | 1/29頁 |
| 文件大?。?/td> | 791K |
| 代理商： | GS8672Q38BE-500I |
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GS8672Q20/38BE-500/450/400
72Mb SigmaQuad-II+TM
Burst of 2 ECCRAMTM
500 MHz–400 MHz
1.8 V VDD
1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.00 4/2011
1/29
2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
Features
2.5 Clock Latency
On-Chip ECC with virtually zero SER
Simultaneous Read and Write SigmaQuad Interface
JEDEC-standard package
Dual Double Data Rate interface
Byte Write Capability
Burst of 2 Read and Write
On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) outputs
1.8 V +100/–100 mV core power supply
1.5 V HSTL Interface
Pipelined read operation
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
IEEE 1149.1 JTAG-compliant Boundary Scan
Pin-compatible with 36Mb and144Mb devices
165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaQuad ECCRAM Overview
The GS8672Q20/38BE are built in compliance with the
SigmaQuad-II+ ECCRAM pinout standard for Separate I/O
synchronous ECCRAMs. They are 75,497,472-bit (72Mb)
ECCRAMs. The GS8672Q20/38BE SigmaQuad ECCRAMs
are just one element in a family of low power, low voltage
HSTL I/O ECCRAMs designed to operate at the speeds needed
to implement economical high performance networking
systems.
Clocking and Addressing Schemes
The GS8672Q20/38BE SigmaQuad-II+ ECCRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Because Separate I/O SigmaQuad-II+ B2 RAMs always
transfer data in two packets, A0 is internally set to 0 for the
first read or write transfer, and automatically incremented by 1
for the next transfer. Because the LSB is tied off internally, the
address field of a SigmaQuad-II+ B2 RAM is always one
address pin less than the advertised index depth (e.g., the 4M x
18 has a 512K addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no On-Chip ECC,
which typically have an SER of 200 FITs/Mb or more. SER
quoted above is based on reading taken at sea level.
However, the On-Chip Error Correction (ECC) will be
disabled if a “Half Write” operation is initiated. See the Byte
Write Contol section for further information.
Parameter Synopsis
-500
-450
-400
tKHKH
2.0 ns
2.2 ns
2.5 ns
tKHQV
0.45 ns
0.45ns
0.45 ns
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相關(guān)代理商/技術(shù)參數(shù) |
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| GS8672T18BE-250 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
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| GS8672T18BE-333 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8672T18BE-333I | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8672T19BE-333 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
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