參數(shù)資料
型號(hào)： GS8662R09BD-350
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, FPBGA-165
文件頁(yè)數(shù)： 37/37頁(yè)
文件大?。?/td> 769K
代理商： GS8662R09BD-350
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time
BW0
BW1
D0–D8
D9–D17
Beat 1
0
1
Data In
Don’t Care
Beat 2
1
0
Don’t Care
Data In
Beat 3
0
Data In
Beat 4
1
0
Don’t Care
Data In
Resulting Write Operation
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Written
Unchanged
Written
Unchanged
Written
Beat 1
Beat 2
Beat 3
Beat 4
GS8662R08/09/18/36BD-400/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 3/2011
9/37
2011, GSI Technology
Output Register Control
SigmaDDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs isare tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaDDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance at mid-rail. The allowable range of RQ to guarantee impedance matching
continuously is between 175
Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is
affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply
voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each
impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output
drivers implemented with discrete binary weighted impedance steps is implemented with discrete binary weighted impedance
steps.
相關(guān)PDF資料
PDF描述
GS8662R09BGD-400I 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165
GS88037BT-225I 256K X 36 CACHE SRAM, 2.5 ns, PQFP100
GS880F36BGT-7.5T 256K X 36 CACHE SRAM, 7.5 ns, PQFP100
GS880V18BT-250T 512K X 18 CACHE SRAM, 5.5 ns, PQFP100
GS880Z32CGT-250 256K X 32 ZBT SRAM, 5.5 ns, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8662R09BD-400 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8662R09E-167 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM
GS8662R09E-167I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM
GS8662R09E-200 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM
GS8662R09E-200I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM
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