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參數(shù)資料
| 型號(hào)： | GS8662D36BD-300IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 2M X 36 STANDARD SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 13 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁(yè)數(shù)： | 34/35頁(yè) |
| 文件大?。?/td> | 755K |
| 代理商： | GS8662D36BD-300IT |
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GS8662D08/09/18/36BD-400/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 3/2011
8/35
2011, GSI Technology
SigmaQuad-II B4 SRAM DDR Write
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on
the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous
command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge
of K, and finally by the next rising edge of K.
Write A
NOP
Read B
Write C
Read D
Write E
NOP
A
B
C
D
E
A
A+3
C
B
B+1
B+2
B+3
D
D+1
D+2
K
Address
R
W
BWx
D
C
Q
CQ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8662DT10BGD-400IT | 8M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| GS8662Q18BD-357 | 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662Q18BGD-357IT | 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662Q18GE-167IT | 4M X 18 STANDARD SRAM, 0.5 ns, PBGA165 |
| GS8662R09BD-350 | 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8662D36BD-333 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662D36BD-350 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662D36BD-400 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662D36E-167 | 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM |
| GS8662D36E-167I | 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM |
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