- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄173638 > GS8662D36BD-300IT (GSI TECHNOLOGY) 2M X 36 STANDARD SRAM, 0.45 ns, PBGA165 PDF資料下載
參數(shù)資料
| 型號(hào)： | GS8662D36BD-300IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 2M X 36 STANDARD SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 13 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁(yè)數(shù)： | 20/35頁(yè) |
| 文件大?。?/td> | 755K |
| 代理商： | GS8662D36BD-300IT |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)當(dāng)前第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)
ID Register Contents
See BSDL Model
GSI Technology
JEDEC Vendor
ID Code
Presence
Register
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
X X X X X X X X X X X X X X X X X X X X 0
0 0 1 1 0 1 1 0 0 1
1
GS8662D08/09/18/36BD-400/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 3/2011
27/35
2011, GSI Technology
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8662DT10BGD-400IT | 8M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| GS8662Q18BD-357 | 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662Q18BGD-357IT | 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662Q18GE-167IT | 4M X 18 STANDARD SRAM, 0.5 ns, PBGA165 |
| GS8662R09BD-350 | 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8662D36BD-333 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662D36BD-350 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662D36BD-400 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8662D36E-167 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM |
| GS8662D36E-167I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。