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    參數(shù)資料
    型號(hào): GS8640FZ18T-8IVT
    廠商: GSI TECHNOLOGY
    元件分類: SRAM
    英文描述: 4M X 18 ZBT SRAM, 8 ns, PQFP100
    封裝: TQFP-100
    文件頁(yè)數(shù): 3/19頁(yè)
    文件大?。?/td> 456K
    代理商: GS8640FZ18T-8IVT
    GS8640FZ18/36T-xxxV
    Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
    Rev: 1.00a 2/2009
    11/19
    2007, GSI Technology
    Note:
    Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
    Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
    this component.
    Absolute Maximum Ratings
    (All voltages reference to VSS)
    Symbol
    Description
    Value
    Unit
    VDD
    Voltage on VDD Pins
    –0.5 to 4.6
    V
    VDDQ
    Voltage on VDDQ Pins
    –0.5 to VDD
    V
    VI/O
    Voltage on I/O Pins
    –0.5 to VDDQ +0.5 ( 4.6 V max.)
    V
    VIN
    Voltage on Other Input Pins
    –0.5 to VDD +0.5 ( 4.6 V max.)
    V
    IIN
    Input Current on Any Pin
    +/–20
    mA
    IOUT
    Output Current on Any I/O Pin
    +/–20
    mA
    PD
    Package Power Dissipation
    1.5
    W
    TSTG
    Storage Temperature
    –55 to 125
    oC
    TBIAS
    Temperature Under Bias
    –55 to 125
    oC
    Power Supply Voltage Ranges (1.8 V/2.5 V Version)
    Parameter
    Symbol
    Min.
    Typ.
    Max.
    Unit
    Notes
    1.8 V Supply Voltage
    VDD1
    1.7
    1.8
    2.0
    V
    2.5 V Supply Voltage
    VDD2
    2.3
    2.5
    2.7
    V
    1.8 V VDDQ I/O Supply Voltage
    VDDQ1
    1.7
    1.8
    VDD
    V
    2.5 V VDDQ I/O Supply Voltage
    VDDQ2
    2.3
    2.5
    VDD
    V
    Notes:
    1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
    tions quoted are evaluated for worst case in the temperature range marked on the device.
    2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
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