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參數(shù)資料
| 型號(hào)： | GS8640FZ18T-8IVT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 4M X 18 ZBT SRAM, 8 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 1/19頁(yè) |
| 文件大小： | 456K |
| 代理商： | GS8640FZ18T-8IVT |
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GS8640FZ18/36T-xxxV
72Mb Flow Through
Synchronous NBT SRAM
6.5 ns–8.0 ns
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.00a 2/2009
1/19
2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
flow through NtRAM, NoBL and ZBT SRAMs
1.8 V or 2.5 V core power supply
1.8 V or 2.5 V I/O supply
LBO pin for Linear or Interleave Burst mode
Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 100-lead TQFP package
RoHS-compliant 100-lead TQFP package available
Functional Description
The GS8640FZ18/36T-xxxV is a 72Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other flow through read/single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the
need to insert deselect cycles when the device is switched from
read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8640FZ18/36T-xxxV is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Parameter Synopsis
-6.5
-7.5
-8.0
Unit
Flow Through
2-1-1-1
tKQ
tCycle
6.5
7.5
8.0
ns
Curr (x18)
Curr (x32/x36)
245
280
220
250
210
240
mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8642Z36GF-167T | 2M X 36 ZBT SRAM, 8 ns, PBGA165 |
| GS8642ZV36E-167IT | 2M X 36 ZBT SRAM, 8 ns, PBGA165 |
| GS8662D11BGD-400 | 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662D36BD-300IT | 2M X 36 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662DT10BGD-400IT | 8M X 9 QDR SRAM, 0.45 ns, PBGA165 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8640FZ36GT-5.5 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 72MBIT 2MX36 5.5NS 100TQFP - Trays |
| GS8640FZ36GT-6.5 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 72MBIT 2MX36 6.5NS 100TQFP - Trays |
| GS8640FZ36GT-7.5 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 72MBIT 2MX36 7.5NS 100TQFP - Trays |
| GS8640FZ36GT-8.0 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 72MBIT 2MX36 8NS 100TQFP - Trays |
| GS8640FZ36GT-8.0I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 72MBIT 2MX36 8NS 100TQFP - Trays |
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