參數(shù)資料
型號(hào): GS840E18GB-100T
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 256K X 18 CACHE SRAM, 12 ns, PBGA119
封裝: BGA-119
文件頁(yè)數(shù): 31/31頁(yè)
文件大?。?/td> 629K
代理商: GS840E18GB-100T
Rev: 2.05 6/2000
9/31
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
.
GS840E18/32/36T/B-180/166/150/100
BGA Pin Description
Pin Location
Symbol
Type
Description
N4, P4
A0, A1
I
Address field LSB’s and Address Counter Preset Inputs.
A2, A3, A5, A6, B3, B5, C2, C3, C5,
C6, R2, R6, T3, T5
An
I
Address Inputs
T4
An
Address Input (x32/36 Versions)
T2, T6
NC
-
No Connect (x32/36 Versions)
T2, T6
An
I
Address Input (x18 Version)
K7, K6, L7, L6, M6, N7, N6, P7
H7, H6, G7, G6, F6, E7, E6, D7
H1, H2, G1, G2, F2, E1, E2, D1
K1, K2, L1, L2, M2, N1, N2, P1
DQA1-DQA8
DQB1-DQB8
DQC1-DQC8
DQD1-DQD8
I/O
Data Input and Output pins. (x32/36 Versions)
P6, D6, D2, P2
DQA9, DQB9,
DQC9, DQD9
I/O
Data Input and Output pins. (x36 Version)
P6, D6, D2, P2
NC
-
No Connect (x32 Version)
L5, G5, G3, L3
BA, BB, BC, BD
I
Byte Write Enable for DQA, DQB, DQC, DQD I/O’s. Active Low. ( x36 Version)
P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2
DQA1-DQA9
DQB1-DQB9
I/O
Data Input and Output pins. (x18 Version)
L5, G3
BA, BB
I
Byte Write Enable for DQA, DQB I/O’s. Active Low. ( x18 Version)
B1, C1, R1, T1, U2, J3, U3, D4, L4,
U4, J5, U5, U6, B7, C7, R7
NC
-
No Connect
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, B1, E1, F2, G1, H2, K1, L2, N2,
P1, G5, L3, T4
NC
-
No Connect (x18 Version)
K4
CK
I
Clock Input Signal. Active High.
M4
BW
I
Byte Write. Writes all enabled bytes. Active Low.
H4
GW
I
Global Write Enable. Writes all bytes. Active Low.
E4, B6
E1, E3
I
Chip Enable. Active Low.
B2
E2
I
Chip Enable. Active High.
F4
G
I
Output Enable. Active Low.
G4
ADV
I
Burst address counter advance enable. Active Low.
A4, B4
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller). Active Low.
T7
ZZ
I
Sleep Mode control. Active High.
R5
FT
I
Flow Through or Pipeline mode. Active Low.
R3
LBO
I
Linear Burst Order mode. Active Low.
J2, C4, J4, R4, J6
VDD
I
Core power supply.
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
VSS
I
I/O and Core Ground.
A1, F1, J1, M1, U1, A7, F7, J7, M7,
U7
VDDQ
I
Output driver power supply.
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