參數(shù)資料
型號: GS8171DW72AGC-350IT
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 256K X 72 STANDARD SRAM, 1.7 ns, PBGA209
封裝: 14 X 22 MM, 1 MM PITCH, LEAD FREE, BGA-209
文件頁數(shù): 6/33頁
文件大小: 1041K
代理商: GS8171DW72AGC-350IT
GS8171DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
14/33
2003, GSI Technology
Common I/O State Diagram
Notes:
1. The notation “X,X,X,X” controlling the state transitions above indicate the states of inputs E1, E, ADV, and W respectively.
2. If (E2 = EP2 and E3 = EP3) then E = “T” else E = “F”.
3. “1” = input “high”; “0” = input “l(fā)ow”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
Deselect
Bank
Deselect
Read
Write
Continue
X,F,0,X or X,X,1,X
Continue
X,F,0,X
1,T,0,X
X,F,0,X
1,T,0,X
X,F,0,X
1,T,0,X
1,T,0,X or X,X,1,X
0,T,0,0
0,T,0,1
0,T,0,0
0,T,0,1
X,F,0,X
0,T,0,0
0,T,0,1
X,X,1,X
0,T,0,0
0,T,0,1
1,T,0,X
0,T,0,0
0,T,0,1
X,X,1,X
0,T,0,1
0,T,0,0
Clock (CK)
Command
Current State
Next State
Current State & Next State Definition for Read
/Write Control State Diagram
Current State (n)
Next State (n + 1)
Transition
Input Command Code
Key
n
n+1
n+2
n+3
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