參數(shù)資料
型號(hào)： GS8171DW72AGC-350IT
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 256K X 72 STANDARD SRAM, 1.7 ns, PBGA209
封裝： 14 X 22 MM, 1 MM PITCH, LEAD FREE, BGA-209
文件頁(yè)數(shù)： 28/33頁(yè)
文件大?。?/td> 1041K
代理商： GS8171DW72AGC-350IT
GS8171DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
4/33
2003, GSI Technology
Operation Control
All address, data and control inputs (with the exception of EP2, EP3, ZQ, and the mode pins, L6, M6, and J6) are synchronized to
rising clock edges. Data in is captured on both rising and falling edges of CK. Read and write operations must be initiated with the
Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of
the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. It should be noted
that ONLY deactivation of the RAM via E2 and/or E3 deactivates the Echo Clocks, CQ1–CQ2.
Pin Description Table
Symbol
Description
Type
Comments
A
Address
Input
—
ADV
Advance
Input
Active High
Bx
Byte Write Enable
Input
Active Low
W
Write Enable
Input
Active Low
E1
Chip Enable
Input
Active Low
E2 & E3
Chip Enable
Input
Programmable Active High or Low
EP2 & EP3
Chip Enable Program Pin
Mode Input
To be tied directly to VDD, VDDQ or VSS
CK
Clock
Input
Active High
CK
Clock
Input
Active Low
HSTL I/O Versions Only
CQ, CQ
Echo Clock
Output
Three State - Deselect via E2 or E3 False
DQ
Data I/O
Input/Output
Three State
MCH
Must Connect High
Input
Active High
To be tied directly to VDD or VDDQ
MCL
Must Connect Low
Input
Active Low
To be tied directly to VSS
ZQ
Output Impedance Control
Analog Input
To be tied to VSS via RQ
TCK
Test Clock
Input
Active High
TDI
Test Data In
Input
—
TDO
Test Data Out
Output
—
TMS
Test Mode Select
Input
—
NC
No Connect
—
Not connected to die or any other pin
VDD
Core Power Supply
Input
1.8 V Nominal
VDDQ
Output Driver Power Supply
Input
1.5 V Nominal
VREF
Input Buffer Reference Voltage
Input
HSTL I/O Versions Only
VSS
Ground
Input
—
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