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參數資料
| 型號： | GS8171DW72AGC-350IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 256K X 72 STANDARD SRAM, 1.7 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, LEAD FREE, BGA-209 |
| 文件頁數： | 5/33頁 |
| 文件大?。?/td> | 1041K |
| 代理商： | GS8171DW72AGC-350IT |
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GS8171DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
13/33
2003, GSI Technology
Double Late Write, Pipelined Read Truth Table
CK
E1
(tn)
E
(tn)
ADV
(tn)
W
(tn)
B
(tn)
Previous
Operation
Current Operation
DQ/CQ
(tn)
DQ/CQ
(tn+1)
DQ/CQ
(tn+2)
0→1
X
F
0
X
Bank Deselect
***/***
Hi-Z/Hi-Z
---
0→1
X
1
X
Bank Deselect Bank Deselect (Continue)
Hi-Z/Hi-Z
---
0→1
1
T
0
X
Deselect
***/***
Hi-Z/CQ
---
0→1
X
1
X
Deselect
Deselect (Continue)
Hi-Z/CQ
---
0→1
0
T
0
T
X
Write
Loads new address
Stores DQx if Bx = 0
***/***
D1/CQ
0→1
0
T
0
F
X
Write (Abort)
Loads new address
No data stored
***/***
Hi-Z/CQ
0→1
X
1
X
T
Write
Write Continue
Increments address by 1
Stores DQx if Bx = 0
***/***
Dn-1/CQ
Dn/CQ
0→1
X
1
X
F
Write
Write Continue (Abort)
Increments address by 1
No data stored
***/***
Dn-1/CQ
Hi-Z/CQ
0→1
0
T
0
1
X
Read
Loads new address
***/***
Q1/CQ
---
0→1
X
1
X
Read
Read Continue
Increments address by 1
Qn-1/CQ
Qn/CQ
---
Notes:
1. If E2 = EP2 and E3 = EP3, then E = “T” else E = “F”.
2. If one or more Bx = 0, then B = “T” else B = “F”.
3. “1” = input “high”; “0” = input “l(fā)ow”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
4. “***” indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation.
5.
“---” indicates that the DQ input requirement / output state and CQ output state are determined by the next operation.
6. DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
7. CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.
8. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces
of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial exter-
nal (base) address.
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