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參數(shù)資料
| 型號： | GS8171DW72AGC-350IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 256K X 72 STANDARD SRAM, 1.7 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, LEAD FREE, BGA-209 |
| 文件頁數(shù)： | 4/33頁 |
| 文件大?。?/td> | 1041K |
| 代理商： | GS8171DW72AGC-350IT |
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GS8171DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
12/33
2003, GSI Technology
.
HSTL Output Driver Impedance Control
HSTL I/O SigmaRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an
external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value
of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-
specified tolerance is between 150
and 300. Periodic readjustment of the output driver impedance is necessary as the
impedance is affected by drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance
evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time
towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Impedance updates
for “0s” occur whenever the SRAM is driving “1s” for the same DQs (and vice-versa for “1s”) or the SRAM is in HI-Z. The
SRAM requires 32K start-up cycles, selected or deselected, after VDD reaches its operating range to reach its programmed output
driver impedance.
Pipelined Read Bank Switch with E1 Deselect
Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
QD
QC
CQ
Bank 1
CQ1 + CQ2
CQ
Bank 2
DQ
Bank 2
QA
Address
A
XX
ADV
/E1
/E2 Bank 1
E2 Bank 2
DQ
Bank 1
F
DE
C
Read
CK
Read
No Op
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