參數(shù)資料
型號(hào)： GS8170S36
廠商： GSI TECHNOLOGY
英文描述： 16Mb（512K x 36Bit）Synchronous SRAM(16M位（512K x 36位）同步靜態(tài)RAM)
中文描述： 16Mb的（為512k × 36Bit）同步SRAM（1,600位（為512k × 36位）同步靜態(tài)內(nèi)存）
文件頁(yè)數(shù)： 16/38頁(yè)
文件大小： 934K
代理商： GS8170S36
Rev: 1.01 11/2000
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
16/38
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8170S18/36/72B-333/300/275/250
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data.
Deselection of the RAM via E1 does not deactivate the
Echo Clocks.
Programmable Enables
Σ
RAMs feature two user-programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active
low or active high inputs, is determined by the state of the programming inputs, PE2 and PE3. For example, if PE2 is held at V
DD
,
E2 functions as an active high enable. If PE2 is held to V
SS
, E2 functions as an active low chip enable input.
Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming
the enable inputs of four
Σ
RAMs in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four
Σ
RAMs can be made to look like one larger RAM to the system.
Example Four Bank Depth Expansion Schematic
A
CK
E1
E2
E3
W
DQ
CQ
A
0
–A
n
CK
W
DQ
0
–DQ
n
Bank 0
Bank 1
Bank 2
Bank 3
Bank Enable Truth Table
EP2
V
SS
V
SS
V
DD
V
DD
EP3
V
SS
V
DD
V
SS
V
DD
E2
E3
Bank 0
Bank 1
Bank 2
Bank 3
Active Low
Active Low
Active High
Active High
Active Low
Active High
Active Low
Active High
E1
A
n – 1
A
n
A
0
–A
n – 2
A
n – 1
A
n
A
0
–A
n – 2
A
n – 1
A
n
A
0
–A
n – 2
A
n – 1
A
n
A
0
–A
n – 2
A
CK
E2
E3
W
DQ
CQ
A
CK
E2
E3
W
DQ
CQ
A
CK
E2
E1
E3
W
DQ
CQ
E1
E1
CQ
相關(guān)PDF資料
PDF描述
GS8170S18 16Mb（1M x 18Bit）Synchronous SRAM(16M位（1M x 18位）同步靜態(tài)RAM)
GS8170S72 16Mb（256K x 72Bit）Synchronous SRAM(16M位（256K x 72位）同步靜態(tài)RAM)
GS8180D09 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
GS8180D18 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
GS8180S36 512K x 36Bit Separate I/O Sigma DDR SRAM(512K x 36位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8171DW36AC-300I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays
GS8171DW36AC-350 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays
GS8171DW36AC-350I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209BGA - Trays
GS8171DW36AGC-250 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays
GS8171DW36AGC-300 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays
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