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參數(shù)資料
| 型號： | GS8170DW72AGC-300IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 256K X 72 STANDARD SRAM, 1.8 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, LEAD FREE, BGA-209 |
| 文件頁數(shù)： | 30/32頁 |
| 文件大?。?/td> | 1038K |
| 代理商： | GS8170DW72AGC-300IT |
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GS8170DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
7/32
2003, GSI Technology
Two Byte Write Control Example with Double Late Write SigmaRAM
Special Functions
Burst Cycles
Although SRAMs can sustain 100% bus bandwidth by eliminating the bus turnaround cycle in Double Late Write mode, burst read
or burst write cycles may also be performed. SRAMs provide an on-chip burst address generator that can be utilized, if desired, to
simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the
internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in
a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.
DA
DB
DE
DA
DC
/BB
DQA0-DQA8
DQB0-DQB8
CQ
/E1
ADV
/BA
D
C
Address
A
B
ADV
CK
Write
F
E
Write
Non-Write
Write
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8170DW72AGC-350 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.7NS 209FBGA - Trays |
| GS8170DW72AGC-350I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.7NS 209FBGA - Trays |
| GS8170LW36AC-300I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays |
| GS8170LW36AGC-250 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
| GS8170LW36AGC-250I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
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