參數(shù)資料
型號： GS8162Z72AC-300
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 256K X 72 ZBT SRAM, 5 ns, PBGA209
封裝： 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁數(shù)： 9/36頁
文件大?。?/td> 889K
代理商： GS8162Z72AC-300
Rev: 1.03a 5/2003
17/36
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Preliminary
Power Supply Voltage Ranges
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
3.3 V Supply Voltage
VDD3
3.0
3.3
3.6
V
2.5 V Supply Voltage
VDD2
2.3
2.5
2.7
V
3.3 V VDDQ I/O Supply Voltage
VDDQ3
3.0
3.3
3.6
V
2.5 V VDDQ I/O Supply Voltage
VDDQ2
2.3
2.5
2.7
V
Notes:
1.
The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2.
Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
VDDQ3 Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VIH
2.0
—
VDD + 0.3
V1
VDD Input Low Voltage
VIL
–0.3
—
0.8
V
1
VDDQ I/O Input High Voltage
VIHQ
2.0
—
VDDQ + 0.3
V1,3
VDDQ I/O Input Low Voltage
VILQ
–0.3
—
0.8
V
1,3
Notes:
1.
The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2.
Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3.
VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
VDDQ2 Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VIH
0.6*VDD
—
VDD + 0.3
V1
VDD Input Low Voltage
VIL
–0.3
—
0.3*VDD
V1
VDDQ I/O Input High Voltage
VIHQ
0.6*VDD
—
VDDQ + 0.3
V1,3
VDDQ I/O Input Low Voltage
VILQ
–0.3
—
0.3*VDD
V1,3
Notes:
1.
The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2.
Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3.
VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
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