參數(shù)資料
型號(hào): GS8162Z72AC-300
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 256K X 72 ZBT SRAM, 5 ns, PBGA209
封裝: 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁(yè)數(shù): 14/36頁(yè)
文件大小: 889K
代理商: GS8162Z72AC-300
Rev: 1.03a 5/2003
21/36
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18A(B/D)/GS8162Z36A(B/D)/GS8162Z72A(C)
Preliminary
AC Electrical Characteristics
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as
specified above.
Parameter
Symbol
-300
-250
-200
-150
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Pipeline
Clock Cycle Time
tKC
3.3
4.0
5.0
6.7
ns
Clock to Output Valid (x18/x36)
tKQ
2.5
2.5
3.0
3.8
ns
Clock to Output Valid (x72)
tKQ
2.8
3.0
3.0
3.8
ns
Clock to Output Invalid
tKQX
1.5
1.5
1.5
1.5
ns
Clock to Output in Low-Z
tLZ1
1.5
1.5
1.5
1.5
ns
Setup time
tS
1.0
1.2
1.4
1.5
ns
Hold time
tH
0.1
0.2
0.4
0.5
ns
Flow Through
Clock Cycle Time
tKC
5.0
5.5
6.5
7.5
ns
Clock to Output Valid
tKQ
5.0
5.5
6.5
7.5
ns
Clock to Output Invalid
tKQX
3.0
3.0
3.0
3.0
ns
Clock to Output in Low-Z
tLZ1
3.0
3.0
3.0
3.0
ns
Setup time
tS
1.4
1.5
1.5
1.5
ns
Hold time
tH
0.4
0.5
0.5
0.5
ns
Clock HIGH Time
tKH
1.3
1.3
1.3
1.5
ns
Clock LOW Time
tKL
1.5
1.5
1.5
1.7
ns
Clock to Output in
High-Z
(x18/x36)
tHZ1
1.5
2.5
1.5
2.5
1.5
3.0
1.5
3.0
ns
Clock to Output in
High-Z
(x72)
tHZ1
1.5
2.8
1.5
3.0
1.5
3.0
1.5
3.0
ns
G to Output Valid
(x18/x36)
tOE
2.5
2.5
3.0
3.8
ns
G to Output Valid
(x72)
tOE
2.8
3.0
3.0
3.8
ns
G to output in Low-Z
tOLZ1
0
0
0
0
ns
G to output in High-Z
(x18/x36)
tOHZ1
2.5
2.5
3.0
3.8
ns
G to output in High-Z
(x72)
tOHZ1
2.8
3.0
3.0
3.8
ns
ZZ setup time
tZZS2
5
5
5
5
ns
ZZ hold time
tZZH2
1
1
1
1
ns
ZZ recovery
tZZR
20
20
20
20
ns
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