參數(shù)資料
型號: GS8160E18AT-300
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 1M X 18 CACHE SRAM, 5 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 3/23頁
文件大?。?/td> 482K
代理商: GS8160E18AT-300
Rev: 1.03a 5/2003
11/23
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160E18/32/36AT-300/250/200/150
Preliminary
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
WR
R
W
R
X
CR
R
CW
CR
W
CW
W
CW
Simplified State Diagram with G
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
相關(guān)PDF資料
PDF描述
GS8160V18AGT-150IT 1M X 18 CACHE SRAM, 7.5 ns, PQFP100
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