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參數(shù)資料
| 型號(hào)： | GS8161E36AT-300IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 CACHE SRAM, 5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 1/34頁(yè) |
| 文件大?。?/td> | 701K |
| 代理商： | GS8161E36AT-300IT |
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Rev: 1.03a 5/2003
1/34
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
GS8161E18A(T/D)/GS8161E32A(D)/GS8161E36A(T/D)
1M x 18, 512K x 36, 512K x 36
18Mb Sync Burst SRAMs
300 MHz–150 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
Preliminary
Features
FT pin for user-configurable flow through or pipeline opera-
tion
Dual Cycle Deselect (DCD) operation
IEEE 1149.1 JTAG-compatible Boundary Scan
2.5 V or 3.3 V +10%/–10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP package
Functional Description
Applications
The GS8161E18A(T/D)/GS8161E32A(D)/GS8161E36A(T/D)
is a 18,874,368-bit high performance synchronous SRAM with
a 2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be
initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode pin
low places the RAM in Flow Through mode, causing output
data to bypass the Data Output Register. Holding FT high
places the RAM in Pipeline mode, activating the rising-edge-
triggered Data Output Register.
DCD Pipelined Reads
The GS8161E18A(T/D)/GS8161E32A(D)/GS8161E36A(T/D)
is a DCD (Dual Cycle Deselect) pipelined synchronous
SRAM. SCD (Single Cycle Deselect) versions are also
available. DCD SRAMs pipeline disable commands to the
same degree as read commands. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8161E18A(T/D)/GS8161E32A(D)/GS8161E36A(T/D)
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V
and 2.5 V compatible. Separate output power (VDDQ) pins are
used to decouple output noise from the internal circuits and are
3.3 V and 2.5 V compatible.
Parameter Synopsis
-300
-250
-200
-150
Unit
Pipeline
3-1-1-1
tKQ(x18/x36)
tCycle
2.5
3.3
2.5
4.0
3.0
5.0
3.8
6.7
ns
Curr (x18)
Curr (x32/x36)
335
390
280
330
230
270
185
210
mA
Flow Through
2-1-1-1
tKQ
tCycle
5.0
5.5
6.5
7.5
ns
Curr (x18)
Curr (x32/x36)
230
270
210
240
185
205
170
190
mA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8161E36BD-150 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 165FBGA - Trays |
| GS8161E36BD-150I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 165FBGA - Trays |
| GS8161E36BD-150IV | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 18MBIT 512KX36 7.5NS/3.8NS 165FPBGA - Trays |
| GS8161E36BD-150V | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 18MBIT 512KX36 7.5NS/3.8NS 165FPBGA - Trays |
| GS8161E36BD-200 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 6.5NS/3NS 165FBGA - Trays |
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