參數(shù)資料
型號: GS8160E18AT-300
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 1M X 18 CACHE SRAM, 5 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 2/23頁
文件大?。?/td> 482K
代理商: GS8160E18AT-300
Rev: 1.03a 5/2003
10/23
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160E18/32/36AT-300/250/200/150
Preliminary
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
WR
R
WR
X
Simple
Synchronous
Operation
Simple
Burst
Synchronou
sOperation
CR
R
CW
CR
Simplified State Diagram
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW)
control inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
相關(guān)PDF資料
PDF描述
GS8160V18AGT-150IT 1M X 18 CACHE SRAM, 7.5 ns, PQFP100
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