參數(shù)資料
型號(hào)： GS8160V36BGT-150I
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 512K X 36 CACHE SRAM, 7.5 ns, PQFP100
封裝： LEAD FREE, TQFP-100
文件頁(yè)數(shù)： 1/23頁(yè)
文件大小： 593K
代理商： GS8160V36BGT-150I
GS8160V18/32/36BT-250/200/150
1M x 18, 512K x 32, 512K x 36
18Mb Sync Burst SRAMs
250 MHz–150 MHz
1.8 V VDD
1.8 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Preliminary
Rev: 1.00 9/2004
1/23
2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
FT pin for user-configurable flow through or pipeline
operation
Single Cycle Deselect (SCD) operation
1.8 V +10%/–10% core power supply
1.8 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP package
Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS8160V18/32/36BT is an 18,874,368-bit (16,777,216-
bit for x32 version) high performance synchronous SRAM
with a 2-bit burst address counter. Although of a type
originally developed for Level 2 Cache applications supporting
high performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8160V18/32/36BT operates on a 1.8 V power supply.
All input are 1.8 V compatible. Separate output power (VDDQ)
pins are used to decouple output noise from the internal circuits
and are 1.8 V compatible.
Parameter Synopsis
-250
-200
-150
Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.5
4.0
3.0
5.0
3.8
6.7
ns
Curr (x18)
Curr (x32/x36)
280
330
230
270
185
210
mA
Flow Through
2-1-1-1
tKQ
tCycle
5.5
6.5
7.5
ns
Curr (x18)
Curr (x32/x36)
210
240
185
205
170
190
mA
相關(guān)PDF資料
PDF描述
GS8160ZV18AGT-150I 1M X 18 ZBT SRAM, 7.5 ns, PQFP100
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8160V36CGT-250 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
GS8160V36CGT-250I 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
GS8160V36CGT-300 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
GS8160V36CGT-300I 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
GS8160V36CGT-333 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
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