參數(shù)資料
型號(hào): GS8160V36BGT-150I
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 512K X 36 CACHE SRAM, 7.5 ns, PQFP100
封裝: LEAD FREE, TQFP-100
文件頁數(shù): 2/23頁
文件大小: 593K
代理商: GS8160V36BGT-150I
GS8160V18/32/36BT-250/200/150
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
10/23
2004, GSI Technology
Simplified State Diagram
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
WR
R
WR
X
Simple
Synchronous
Operation
Simple
Burst
Synchronou
sOperation
CR
R
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW)
control inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
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